公开(公告)号：US20230268241A1

公开(公告)日：2023-08-24

申请号：US18140907

申请日：2023-04-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaehoon CHOI ,  Sayoon Kang ,  Taewook Kim ,  Hwasub Oh ,  Jooyung Chol

IPC: H01L23/34 ,  H01L23/495 ,  H01L23/00 ,  H01L23/28 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L23/34 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49568 ,  H01L24/14 ,  H01L23/28 ,  H01L23/5384 ,  H01L25/0657 ,  H01L23/49575

Abstract: A semiconductor package includes a connection structure having first and second surfaces opposing each other and including a first redistribution layer; a semiconductor chip disposed on the first surface of the connection structure and including connection pads connected to the first redistribution layer; an encapsulant disposed on the first surface of the connection structure and encapsulating the semiconductor chip; and a second redistribution layer disposed on the encapsulant; a wiring structure connecting the first and second redistribution layers to each other and extending in a stacking direction; and a heat dissipation element disposed on at least a portion of the second surface of the connection structure.

公开(公告)号：US20220108935A1

公开(公告)日：2022-04-07

申请号：US17354291

申请日：2021-06-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eunseok CHO ,  Minjeong GU ,  Joonsung KIM ,  Jaehoon CHOI

IPC: H01L23/367 ,  H01L23/31 ,  H01L23/498 ,  H01L23/552 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L25/18 ,  H01L25/065

Abstract: A semiconductor package includes a base substrate including a wiring pattern, an interposer substrate including lower and upper redistribution patterns, a semiconductor structure, a heat dissipation structure, a plurality of external connection bumps disposed on a lower surface of the base substrate, a plurality of lower connection bumps disposed between the base substrate and the interposer substrate, and a plurality of upper connection bumps disposed between the interposer substrate and the semiconductor structure.

公开(公告)号：US20170358540A1

公开(公告)日：2017-12-14

申请号：US15622708

申请日：2017-06-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byoung-Gug MIN ,  Sungil CHO ,  Jaehoon CHOI ,  Shi-kyung KIM

IPC: H01L23/552

CPC classification number: H01L23/552 ,  H01L21/561 ,  H01L23/295 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/3025 ,  H01L2224/81

Abstract: Semiconductor packages and a methods for manufacturing a semiconductor package are provided. The method includes providing a package including a substrate, a semiconductor chip provided on the substrate, and a molding layer provided on the substrate and covering the semiconductor chip, the substrate including a ground pattern exposed at one surface of the substrate; and applying a solution including metal particles and a conductive carbon material onto the molding layer to form a shielding layer covering the molding layer. The shielding layer includes the metal particles and the conductive carbon material connected to at least one of the metal particles. The shielding layer extends onto the one surface of the substrate and is electrically connected to the ground pattern.

公开(公告)号：US20250069979A1

公开(公告)日：2025-02-27

申请号：US18943337

申请日：2024-11-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eunseok CHO ,  Minjeong GU ,  Joonsung KIM ,  Jaehoon CHOI

IPC: H01L23/367 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/552 ,  H01L25/065 ,  H01L25/18

Abstract: A method of manufacturing a semiconductor package is provided and includes: forming a lower redistribution structure, the lower redistribution structure including lower redistribution patterns having lower connection pads; forming an upper redistribution structure on a boundary surface of the lower redistribution structure, the upper redistribution structure including upper redistribution patterns having upper connection pads electrically connected to the lower connection pads; forming openings exposing at least a portion of each of the lower connection pads; disposing an interposer substrate, including the lower redistribution structure and the upper redistribution structure, on a base substrate, the lower connection pads of the interposer substrate electrically connected to wiring patterns of the base substrate through lower connection bumps disposed on the openings; and disposing at least one of semiconductor chips, including connection pads, on the interposer substrate, the connection pads electrically connected to the upper connection pads through upper connection bumps.

公开(公告)号：US20250046769A1

公开(公告)日：2025-02-06

申请号：US18665893

申请日：2024-05-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jooyoung CHOI ,  Dahee KIM ,  Jeongseok KIM ,  Gyujin CHOI ,  Jaehoon CHOI

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L25/16

Abstract: A semiconductor package may include a package redistribution layer including a plurality of package redistribution patterns and a package redistribution insulating layer surrounding the plurality of package redistribution patterns, a plurality of electronic components apart from each other in a horizontal direction on the package redistribution layer and including at least one sub package, a package molding layer covering a top surface of the package redistribution layer and surrounding the plurality of electronic components, and a plurality of package connection terminals attached to a bottom surface of the package redistribution layer in a fan-out manner. The at least one sub package may include a package substrate, a semiconductor chip attached to the package substrate, and a sub molding layer on the package substrate.