公开(公告)号：US10164806B2

公开(公告)日：2018-12-25

申请号：US15485851

申请日：2017-04-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaehyeok Jang

IPC: H04L25/03 ,  H04L7/04 ,  H04L5/00 ,  H04L27/00

Abstract: A clock data recovery circuit includes; a clock recovery circuit that receives a pseudo random binary sequence (PRBS) pattern and generates a recovery clock by counting edges of the PRBS pattern, and a data recovery circuit that generates recovery data from at least one of the PRBS pattern and externally provided serial data.

公开(公告)号：US20190220288A1

公开(公告)日：2019-07-18

申请号：US16352185

申请日：2019-03-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehyeok Jang ,  Yae Seul LEE ,  Sang-Yong PARK ,  Tae Sun YOU ,  Seong Wook HWANG

IPC: G06F9/4401 ,  G06F13/24 ,  G06F1/3287 ,  G06F13/42 ,  G06F13/40

CPC classification number: G06F9/4418 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3287 ,  G06F13/24 ,  G06F13/4022 ,  G06F13/4291 ,  Y02D10/126 ,  Y02D10/151

Abstract: An integrated circuit device is provided. The integrated circuit device may include a central processing unit (CPU) configured to operate in one of a plurality of modes and a wake-up control circuit configured to control the CPU. The wake-up control circuit may include a clock generator configured to generate an internal clock signal, a multiplexer configured to select a signal from among an external signal and the internal clock signal and to provide the CPU with the selected signal as an operating clock signal, and a controller configured to control the CPU and the clock generator based on the external signal.

公开(公告)号：US10678556B2

公开(公告)日：2020-06-09

申请号：US16352185

申请日：2019-03-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehyeok Jang ,  Yae Seul Lee ,  Sang-Yong Park ,  Tae Sun You ,  Seong Wook Hwang

IPC: G06F1/3287 ,  G06F9/4401 ,  G06F1/324 ,  G06F1/3206 ,  G06F13/24 ,  G06F13/40 ,  G06F13/42

Abstract: An integrated circuit device is provided. The integrated circuit device may include a central processing unit (CPU) configured to operate in one of a plurality of modes and a wake-up control circuit configured to control the CPU. The wake-up control circuit may include a clock generator configured to generate an internal clock signal, a multiplexer configured to select a signal from among an external signal and the internal clock signal and to provide the CPU with the selected signal as an operating clock signal, and a controller configured to control the CPU and the clock generator based on the external signal.

公开(公告)号：US10255079B2

公开(公告)日：2019-04-09

申请号：US15394518

申请日：2016-12-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehyeok Jang ,  Yae Seul Lee ,  Sang-Yong Park ,  Tae Sun You ,  Seong Wook Hwang

IPC: G06F9/00 ,  G06F9/4401 ,  G06F1/3287 ,  G06F13/24 ,  G06F13/40 ,  G06F13/42

Abstract: An integrated circuit device is provided. The integrated circuit device may include a central processing unit (CPU) configured to operate in one of a plurality of modes and a wake-up control circuit configured to control the CPU. The wake-up control circuit may include a clock generator configured to generate an internal clock signal, a multiplexer configured to select a signal from among an external signal and the internal clock signal and to provide the CPU with the selected signal as an operating clock signal, and a controller configured to control the CPU and the clock generator based on the external signal.