公开(公告)号：US20240234000A1

公开(公告)日：2024-07-11

申请号：US18116836

申请日：2023-03-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dmytro APALKOV ,  Roman CHEPULSKYY ,  Jaewoo JEONG ,  FNU IKHTIAR ,  Sungchul LEE

IPC: H01F10/32 ,  G11C11/16 ,  H10B61/00 ,  H10N50/10 ,  H10N50/85

CPC classification number: H01F10/3286 ,  G11C11/161 ,  H10B61/22 ,  H10N50/10 ,  H10N50/85

Abstract: A perpendicular shape anisotropy magnetic tunnel junction structure includes a reference layer, a non-magnetic layer, and a free layer. The reference layer includes a first side and a second side opposite the first side. The non-magnetic spacer includes a first side and a second side. The first side of the non-magnetic spacer is on the second side of the first reference layer. The free layer includes a first side and a second side. The first side of the free layer is on the second side of the non-magnetic spacer. The free layer includes a first layer on the first side of the free layer, a second layer on the second side of the free layer and a coupling layer disposed between the first layer and the second layer. A ratio of a saturation magnetization of the second layer to a saturation magnetization of the first layer ranges from 0.2-0.8 inclusive.

公开(公告)号：US20170338403A1

公开(公告)日：2017-11-23

申请号：US15360221

申请日：2016-11-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woojin KIM ,  Keewon KIM ,  S.P. Stuart PARKIN ,  Jaewoo JEONG ,  Mahesh Govind SAMANT

IPC: H01L43/02 ,  H01L43/10 ,  H01L43/08 ,  H01L43/12 ,  H01F10/32

CPC classification number: H01L43/02 ,  G11C11/161 ,  H01F10/3218 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: Example embodiments relate to magnetic memory devices and methods for manufacturing the same. The magnetic memory device includes a magnetic tunnel junction layer including a first magnetic layer, a second magnetic layer, and a first tunnel barrier layer between the first and second magnetic layers. The second magnetic layer is disposed on the first tunnel barrier layer and is in direct contact with the first tunnel barrier layer. The second magnetic layer includes cobalt-iron-beryllium (CoFeBe). A beryllium content of CoFeBe in the second magnetic layer ranges from about 2 at % to about 15 at %.

公开(公告)号：US20240237543A1

公开(公告)日：2024-07-11

申请号：US18116839

申请日：2023-03-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dmytro APALKOV ,  Roman CHEPULSKYY ,  Jaewoo JEONG ,  FNU IKHTIAR ,  Sungchul LEE

IPC: H10N50/10 ,  G11C11/16 ,  H01F10/32 ,  H10B61/00 ,  H10N50/85

CPC classification number: H10N50/10 ,  G11C11/161 ,  H01F10/3286 ,  H10B61/00 ,  H10N50/85

Abstract: A perpendicular shape anisotropy magnetic tunnel junction structure includes a reference layer, a non-magnetic layer, and a free layer. The reference layer includes a first side and a second side that is opposite the first side of the reference layer. The non-magnetic spacer includes a first side and a second side in which the first side of the non-magnetic spacer is on the second side of the first reference layer. The free layer includes a first side and a second side in which the first side of the free layer is on the second side of the non-magnetic spacer and in which the free layer further includes an exchange energy Aex having a range of 0.5 to 1.0 μerg/cm2.

公开(公告)号：US20230032415A1

公开(公告)日：2023-02-02

申请号：US17722805

申请日：2022-04-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaemin CHOI ,  Yonghun KIM ,  Jaewoo JEONG ,  Kyungryun KIM ,  Yoochang SUNG ,  Changsik YOO

IPC: G11C7/10

Abstract: A semiconductor device includes: a plurality of pads connected to a memory device receiving a data signal using first to fourth clock signals having different phases; a data transmission/reception circuit inputting and outputting the data signal to a plurality of data pads of the plurality of pads and including a data delay cell adjusting a phase of the data signal; a clock output circuit outputting first to fourth clock signals to a plurality of clock pads of the plurality of pads and including first to fourth clock delay cells adjusting phases of the first to fourth clock signals; and a controller adjusting a delay amount of at least one of the first to fourth clock delay cells and the data delay cell so that each of the first to fourth clock signals is aligned with the data signal in the memory device.

公开(公告)号：US20240237542A1

公开(公告)日：2024-07-11

申请号：US18116835

申请日：2023-03-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dmytro APALKOV ,  Roman CHEPULSKYY ,  Jaewoo JEONG ,  FNU IKHTIAR ,  Sungchul LEE

IPC: H10N50/10 ,  G11C11/16 ,  H01F10/32 ,  H10B61/00 ,  H10N50/85

CPC classification number: H10N50/10 ,  G11C11/161 ,  H01F10/3286 ,  H10B61/00 ,  H10N50/85

Abstract: A perpendicular shape anisotropy magnetic tunnel junction structure includes a reference layer, a non-magnetic layer, and a free layer. The reference layer includes a first side and a second side that is opposite the first side. The non-magnetic spacer includes a first side and a second side. The first side of the non-magnetic spacer is on the second side of the first reference layer. The free layer includes a first side and a second side. The first side of the free layer is on the second side of the non-magnetic spacer. The free layer further includes a first layer on the first side of the free layer, a second layer on the second side of the free layer and a coupling layer disposed between the first layer and the second layer. A saturation magnetization of the second layer is between 2-5 times inclusive a saturation magnetization of the first layer.

公开(公告)号：US20240144991A1

公开(公告)日：2024-05-02

申请号：US18326657

申请日：2023-05-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaewoo JEONG ,  Yonghun KIM ,  Kihan KIM ,  Changsik YOO

IPC: G11C11/4076 ,  G06F1/10 ,  G06F1/12

CPC classification number: G11C11/4076 ,  G06F1/10 ,  G06F1/12

Abstract: A memory device includes a multi-phase clock generator configured to generate first to N-th clock signals having N different phases based on a clock signal from the memory controller, and a monitoring clock signal generator configured to generate a monitoring clock signal having a logic state corresponding to a data pattern in synchronization with edges of the first to N-th clock signals, wherein the monitoring clock signal includes a first monitoring clock signal configured to detect a skew between the first and third clock signals in a first step of a training operation, a second monitoring clock signal configured to detect a skew between the second and fourth clock signals in a second step of the training operation, and a third monitoring clock signal configured to detect a skew between the first and second clock signals in a third step of the training operation.

公开(公告)号：US20130153286A1

公开(公告)日：2013-06-20

申请号：US13710956

申请日：2012-12-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeongung KIM ,  Jaewoo JEONG ,  Kuntak KIM ,  Hyunjoo HAN ,  Seyoung JANG

IPC: H05K9/00 ,  H05K3/00

CPC classification number: H05K9/0007 ,  H05K3/00 ,  H05K9/0028 ,  Y10T29/49124

Abstract: A shielding system for a mobile device and a method for assembling the system are provided. The shielding system includes a Printed Circuit Board (PCB) with a first area and a thickness, and a shield enclosure, spaced apart and above a front side of the PCB at a certain distance, for enclosing components on the PCB. Parts of the shield enclosure are coupled to at least one of a lateral side and a back side of the PCB.

Abstract translation: 提供了一种用于移动设备的屏蔽系统和用于组装该系统的方法。 屏蔽系统包括具有第一区域和厚度的印刷电路板（PCB）和屏蔽外壳，隔离并且在PCB的正面上方一定距离，用于封装PCB上的部件。 屏蔽外壳的部分耦合到PCB的侧面和背面中的至少一个。