公开(公告)号：US12020765B2

公开(公告)日：2024-06-25

申请号：US17409154

申请日：2021-08-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji Woon Park ,  Joon Ki Paek

IPC: G11C5/06 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

CPC classification number: G11C5/06 ,  H01L23/49816 ,  H01L23/5386 ,  H01L25/0652 ,  H01L25/0657 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00 ,  H01L2225/06506 ,  H01L2225/06562

Abstract: Provided is a non-volatile memory package that is electrically optimized with a plurality of different non-volatile memory chips through a ball map, by fixing positions of buffer chips connected to the plurality of different non-volatile memory chips.

公开(公告)号：US11423950B2

公开(公告)日：2022-08-23

申请号：US16885832

申请日：2020-05-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji Woon Park ,  Jae-Sang Yun

IPC: G11C5/06 ,  G11C5/02 ,  H01L23/00

Abstract: A solid state drive (SSD) device, including a substrate; a first buffer chip disposed on the substrate; a second buffer chip disposed on the first buffer chip; a plurality of first nonvolatile memory chips connected to the second buffer chip through wire bonding; a controller configured to transmit a control signal to the plurality of first nonvolatile memory chips through a first channel; and a first redistribution layer disposed in the substrate and configured to electrically connect the first channel to the first buffer chip, wherein the first buffer chip is connected to the first redistribution layer through flip chip bonding, and the second buffer chip is connected to the first redistribution layer through a first wire.

公开(公告)号：US20240127869A1

公开(公告)日：2024-04-18

申请号：US18317344

申请日：2023-05-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Sang Yun ,  Kwang Soo Park ,  Ji Woon Park ,  Bong Gyu Kang ,  Su-Jin Kim

IPC: G11C7/10 ,  G11C5/06 ,  G11C5/14

CPC classification number: G11C7/1039 ,  G11C5/06 ,  G11C5/14

Abstract: A storage device having a multi drop structure is provided. The storage device comprises a storage controller configured to output a data signal, a first non-volatile memory configured to receive the data signal, a first wiring electrically connected to the storage controller and configured to transfer the data signal, a first termination module including a first impedance element that electrically connects the first wiring to at least one of a power voltage or a ground voltage, a second wiring electrically connected to the first wiring and configured to transfer the data signal to the first non-volatile memory, and a third wiring electrically connected to the first wiring and configured to transfer the data signal to the first termination module.

公开(公告)号：US11881279B2

公开(公告)日：2024-01-23

申请号：US17879479

申请日：2022-08-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji Woon Park ,  Jae-Sang Yun

IPC: G11C5/06 ,  H01L23/00 ,  G11C5/02

CPC classification number: G11C5/06 ,  G11C5/025 ,  H01L24/45

Abstract: A solid state drive (SSD) device, including a substrate; a first buffer chip disposed on the substrate; a second buffer chip disposed on the first buffer chip; a plurality of first nonvolatile memory chips connected to the second buffer chip through wire bonding; a controller configured to transmit a control signal to the plurality of first nonvolatile memory chips through a first channel; and a first redistribution layer disposed in the substrate and configured to electrically connect the first channel to the first buffer chip, wherein the first buffer chip is connected to the first redistribution layer through flip chip bonding, and the second buffer chip is connected to the first redistribution layer through a first wire.

公开(公告)号：US10824580B2

公开(公告)日：2020-11-03

申请号：US15815048

申请日：2017-11-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byung Ho Kim ,  Kwang Soo Park ,  Ji Woon Park

IPC: G06F12/00 ,  G06F13/40 ,  G11C5/02 ,  G11C8/12 ,  G11C7/22 ,  G11C5/06 ,  G06F13/42 ,  G11C5/04 ,  G11C11/4063 ,  G11C7/10 ,  G06F13/16 ,  G11C29/02

Abstract: A semiconductor device includes a plurality of memory chips arranged in a line on a substrate, and a bus connected to the plurality of memory chips and configured to sequentially supply an electrical signal to the plurality of memory chips in accordance with a fly-by topology. An order in which the electrical signal is supplied to the plurality of memory chips is different from an order in which the plurality of memory chips is arranged in the line on the substrate.