公开(公告)号：US20240321804A1

公开(公告)日：2024-09-26

申请号：US18489886

申请日：2023-10-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dowan Kim ,  Jieun Woo ,  Unbyoung Kang ,  Seokbong Park

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L24/20 ,  H01L21/568 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/19 ,  H01L25/18 ,  H10B80/00 ,  H01L2224/16227 ,  H01L2224/19 ,  H01L2224/2101 ,  H01L2224/215 ,  H01L2224/2201 ,  H01L2924/01004 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/0132 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/14361 ,  H01L2924/1437 ,  H01L2924/1441 ,  H01L2924/1443

Abstract: A semiconductor package a first package unit comprising a semiconductor chip; and a redistribution structure on the first package unit, wherein the redistribution structure comprises a plurality of wiring lines and a plurality of insulating layers on the plurality of wiring lines, wherein the plurality of wiring lines comprise first subset including a plurality of outermost wiring lines and a second subset, wherein a vertical distance between the plurality of outermost wiring lines and the first package unit is greater than a vertical distance between the second subset of the plurality of wiring lines and the first package unit, a respective surface roughness of each of the plurality of outermost wiring lines is different, and the respective surface roughness of each of the plurality of outermost wiring lines is based on a respective width of each of the plurality of outermost wiring lines in a horizontal direction.