公开(公告)号：US12087714B2

公开(公告)日：2024-09-10

申请号：US17589500

申请日：2022-01-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-An Liu ,  Wen-Chiung Tu ,  Yuan-Yang Hsiao ,  Kai Tak Lam ,  Chen-Chiu Huang ,  Zhiqiang Wu ,  Dian-Hau Chen

IPC: H01L23/00

CPC classification number: H01L24/02 ,  H01L2224/02311 ,  H01L2224/02331 ,  H01L2224/02373 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/35121

Abstract: Methods and semiconductor structures are provided. A semiconductor structure according to the present disclosure includes a plurality of transistors, an interconnect structure electrically coupled to the plurality of transistors, a metal feature disposed over the interconnect structure and electrically isolated from the plurality of transistors, an insulation layer disposed over the metal feature, and a first redistribution feature and a second redistribution feature disposed over the insulation layer. A space between the first redistribution feature and the second redistribution feature is disposed directly over at least a portion of the metal feature.

公开(公告)号：US20240290677A1

公开(公告)日：2024-08-29

申请号：US18459111

申请日：2023-08-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gyuseong PARK ,  Joongwon SHIN ,  Jong-Min LEE ,  Jimin CHOI

IPC: H01L23/31 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L23/532

CPC classification number: H01L23/3157 ,  H01L21/56 ,  H01L21/76801 ,  H01L23/3192 ,  H01L23/53295 ,  H01L24/13 ,  H01L23/291 ,  H01L24/05 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05669 ,  H01L2224/05676 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/05686 ,  H01L2224/13021 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13169 ,  H01L2224/13176 ,  H01L2224/13181 ,  H01L2224/13184 ,  H01L2224/13186 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/0496

Abstract: A semiconductor device includes an interlayer insulating layer, a first protective insulating layer on the interlayer insulating layer, a second protective insulating layer on the first protective insulating layer, and insulating structures disposed in at least one of the first protective insulating layer or the second protective insulating layer, wherein the insulating structures include a first insulating structure including a first material having a first physical property, and a second insulating structure including a second material having a second physical property, and the first material and the second material include a same material, and the first physical property and the second physical property are different physical properties.

公开(公告)号：US20240282726A1

公开(公告)日：2024-08-22

申请号：US18170581

申请日：2023-02-17

Applicant: NXP USA, INC.

Inventor： Trent Uehling

IPC: H01L23/00

CPC classification number: H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/03464 ,  H01L2224/03912 ,  H01L2224/0392 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05582 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05686 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2924/014 ,  H01L2924/04953

Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a conductive probe plug on an exposed portion of a die pad of a semiconductor die by way of an electroless plating process. A top surface of the conductive probe plug extends above a top surface of a top passivation layer of the semiconductor die. A copper pillar is formed over the conductive probe plug by way of an electrolytic plating process. Outer sidewalls of the copper pillar surround the top surface of the conductive probe plug. A top surface of the copper pillar is plated with a solder plate material and reflowed to form a solder cap on the top of the copper pillar.

公开(公告)号：US12040296B2

公开(公告)日：2024-07-16

申请号：US17826222

申请日：2022-05-27

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Luguang Wang

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L24/81 ,  H01L2224/1308 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13166 ,  H01L2224/13181 ,  H01L2224/81815 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/04941 ,  H01L2924/04953

Abstract: A semiconductor structure and a method for same are provided. The semiconductor structure includes: a first base having a first face, a second base having a second face, and a welding structure. The first base has an electrical connection column protruding from the first face. A first groove is provided at top of the electrical connection column. A conductive column is provided in the second base, and the second base also has a second groove. A top face and at least portion of a side face of the conductive column are exposed by the second groove. The electrical connection column is partially located in the second groove, and the conductive column is partially located in the first groove. At least portion of the welding structure is filled in the second groove, and at least further portion of the welding structure is filled between the conductive column and first groove.

公开(公告)号：US12027447B2

公开(公告)日：2024-07-02

申请号：US17865256

申请日：2022-07-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Anhao Cheng ,  Chun-Chang Liu

IPC: H01L23/48 ,  H01L21/304 ,  H01L21/768 ,  H01L23/00 ,  H01L23/522 ,  H01L23/525

CPC classification number: H01L23/481 ,  H01L21/304 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76852 ,  H01L21/76873 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/525 ,  H01L24/02 ,  H01L24/11 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02166 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/0233 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/0239 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05571 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2224/05571 ,  H01L2924/00012 ,  H01L2224/0239 ,  H01L2924/01074 ,  H01L2224/0239 ,  H01L2924/01079 ,  H01L2224/0239 ,  H01L2924/01013 ,  H01L2224/0239 ,  H01L2924/01029 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2224/131 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2224/05639 ,  H01L2924/00014 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2224/05624 ,  H01L2924/00014 ,  H01L2224/05166 ,  H01L2924/00014 ,  H01L2224/05181 ,  H01L2924/00014 ,  H01L2224/05186 ,  H01L2924/04941 ,  H01L2224/05186 ,  H01L2924/04953 ,  H01L2224/05124 ,  H01L2924/00014 ,  H01L2224/05184 ,  H01L2924/00014 ,  H01L2224/05144 ,  H01L2924/00014 ,  H01L2224/0345 ,  H01L2924/00014 ,  H01L2224/03452 ,  H01L2924/00014 ,  H01L2224/03462 ,  H01L2924/00014

Abstract: A semiconductor device includes a first conductive element electrically connected to an interconnect structure, wherein the first conductive element includes a first conductive material. The semiconductor device further includes an RDL over the first conductive element and electrically connected to the first conductive element, wherein the RDL includes a second conductive material different from the first conductive material. The semiconductor device further includes a passivation layer over the RDL, wherein a top portion of a sidewall of the second passivation layer includes a convex curve protruding in a direction parallel to a top surface of the interconnect structure, a width of the top portion at a bottom of the convex curve is less than a width of the top portion at a middle of the convex curve, and the middle of the convex curve is above the bottom of the convex curve.

公开(公告)号：US11999001B2

公开(公告)日：2024-06-04

申请号：US17545322

申请日：2021-12-08

Applicant: Adeia Semiconductor Technologies LLC

Inventor： Cyprian Emeka Uzoh

IPC: H05K1/11 ,  B23K20/00 ,  B23K20/02 ,  H01L21/50 ,  H01L23/00 ,  H01L23/10 ,  H01L23/48 ,  H01L23/49 ,  H01L23/498 ,  H05K1/14 ,  H05K1/18 ,  H05K3/00 ,  H05K3/34 ,  H05K13/04 ,  H01L21/48 ,  H01L21/768

CPC classification number: B23K20/023 ,  B23K20/002 ,  H01L21/50 ,  H01L23/10 ,  H01L23/481 ,  H01L23/49 ,  H01L23/49811 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/98 ,  H05K1/11 ,  H05K1/14 ,  H05K1/144 ,  H05K1/18 ,  H05K3/0094 ,  H05K3/34 ,  H05K13/046 ,  H05K13/0465 ,  H01L21/4853 ,  H01L21/76898 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/27 ,  H01L2224/02372 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05023 ,  H01L2224/05025 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/05138 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/0518 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05187 ,  H01L2224/05568 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/13009 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/13076 ,  H01L2224/13078 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13105 ,  H01L2224/13109 ,  H01L2224/13138 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13184 ,  H01L2224/1319 ,  H01L2224/14131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16235 ,  H01L2224/16501 ,  H01L2224/16503 ,  H01L2224/16505 ,  H01L2224/2745 ,  H01L2224/27452 ,  H01L2224/27462 ,  H01L2224/27464 ,  H01L2224/29011 ,  H01L2224/29023 ,  H01L2224/2908 ,  H01L2224/29082 ,  H01L2224/29105 ,  H01L2224/29109 ,  H01L2224/29138 ,  H01L2224/29147 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/32501 ,  H01L2224/32505 ,  H01L2224/73103 ,  H01L2224/73203 ,  H01L2224/81075 ,  H01L2224/8112 ,  H01L2224/81141 ,  H01L2224/81193 ,  H01L2224/81825 ,  H01L2224/83075 ,  H01L2224/8312 ,  H01L2224/83193 ,  H01L2224/83825 ,  H01L2924/00014 ,  H01L2924/381 ,  H05K1/111 ,  H05K2201/04 ,  H05K2203/04 ,  H01L2224/8112 ,  H01L2924/00014 ,  H01L2224/1147 ,  H01L2924/00014 ,  H01L2224/05187 ,  H01L2924/04953 ,  H01L2224/0518 ,  H01L2924/01071 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2224/05181 ,  H01L2924/00014 ,  H01L2224/05171 ,  H01L2924/01042 ,  H01L2224/05138 ,  H01L2924/01015 ,  H01L2924/00014 ,  H01L2224/05184 ,  H01L2924/00014 ,  H01L2224/05164 ,  H01L2924/00014 ,  H01L2224/05187 ,  H01L2924/04941 ,  H01L2224/05155 ,  H01L2924/01015 ,  H01L2224/05157 ,  H01L2924/01015 ,  H01L2224/05166 ,  H01L2924/01074 ,  H01L2224/05155 ,  H01L2924/01074 ,  H01L2224/13105 ,  H01L2924/01047 ,  H01L2224/13109 ,  H01L2924/01031 ,  H01L2924/01047 ,  H01L2224/13138 ,  H01L2924/01034 ,  H01L2224/11462 ,  H01L2924/00014 ,  H01L2224/11464 ,  H01L2924/00014 ,  H01L2224/1145 ,  H01L2924/00014 ,  H01L2224/11452 ,  H01L2924/00014 ,  H01L2224/16501 ,  H01L2924/00012 ,  H01L2224/16505 ,  H01L2924/00012 ,  H01L2224/14131 ,  H01L2924/00014 ,  H01L2224/05026 ,  H01L2924/00012 ,  H01L2224/05571 ,  H01L2924/00012 ,  H01L2224/13155 ,  H01L2924/00014 ,  H01L2224/13184 ,  H01L2924/00014 ,  H01L2224/73103 ,  H01L2924/00012 ,  H01L2224/73203 ,  H01L2924/00012 ,  H01L2224/27462 ,  H01L2924/00014 ,  H01L2224/27464 ,  H01L2924/00014 ,  H01L2224/2745 ,  H01L2924/00014 ,  H01L2224/27452 ,  H01L2924/00014 ,  H01L2224/29105 ,  H01L2924/01047 ,  H01L2224/29109 ,  H01L2924/01031 ,  H01L2924/01047 ,  H01L2224/29138 ,  H01L2924/01034 ,  H01L2224/32501 ,  H01L2924/00012 ,  H01L2224/32505 ,  H01L2924/00012 ,  H01L2224/8312 ,  H01L2924/00014 ,  H01L2224/1319 ,  H01L2924/07025 ,  H01L2924/00014 ,  H01L2224/05552 ,  H01L2224/13018 ,  H01L2924/00012

Abstract: A microelectronic assembly includes a first substrate having a surface and a first conductive element and a second substrate having a surface and a second conductive element. The assembly further includes an electrically conductive alloy mass joined to the first and second conductive elements. First and second materials of the alloy mass each have a melting point lower than a melting point of the alloy. A concentration of the first material varies in concentration from a relatively higher amount at a location disposed toward the first conductive element to a relatively lower amount toward the second conductive element, and a concentration of the second material varies in concentration from a relatively higher amount at a location disposed toward the second conductive element to a relatively lower amount toward the first conductive element.

公开(公告)号：US20240178167A1

公开(公告)日：2024-05-30

申请号：US18437444

申请日：2024-02-09

Applicant: Huawei Technologies Co., Ltd.

Inventor： Ran He ,  Huifang Jiao

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/06 ,  H01L24/08 ,  H01L24/80 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03466 ,  H01L2224/03845 ,  H01L2224/05554 ,  H01L2224/05571 ,  H01L2224/05582 ,  H01L2224/05584 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05686 ,  H01L2224/06517 ,  H01L2224/08145 ,  H01L2224/80357 ,  H01L2224/80896 ,  H01L2924/04642 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/059

Abstract: The invention provide a chip package structure, which includes a first chip and a first hybrid bonding structure. The first chip is connected to another chip through the first hybrid bonding structure. The first hybrid bonding structure includes a first bonding layer. The first bonding layer is disposed on a side away from a substrate of the first chip, and the first bonding layer includes a first insulation material and a plurality of first metal solder pads embedded in the first insulation material. Each of the plurality of first metal solder pads includes a groove structure. A groove bottom of the groove structure is buried in the first insulation material, and a groove opening of the groove structure is exposed to a surface of the first insulation material and is flush with the surface of the first insulation material.

公开(公告)号：US11923326B2

公开(公告)日：2024-03-05

申请号：US17875291

申请日：2022-07-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Ching-Yu Chang ,  Ming-Da Cheng ,  Ming-Hui Weng

IPC: H01L23/00 ,  C08G73/10

CPC classification number: H01L24/05 ,  C08G73/1078 ,  C08G73/1085 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02251 ,  H01L2224/0226 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03616 ,  H01L2224/0401 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05176 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13026 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/1312 ,  H01L2224/13123 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13149 ,  H01L2224/13155 ,  H01L2224/1316 ,  H01L2224/13166 ,  H01L2224/13171 ,  H01L2224/13179 ,  H01L2224/1318 ,  H01L2224/13181 ,  H01L2224/13184 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/07025

Abstract: A method of manufacturing a bump structure includes forming a passivation layer over a substrate. A metal pad structure is formed over the substrate, wherein the passivation layer surrounds the metal pad structure. A polyimide layer including a polyimide is formed over the passivation layer and the metal pad structure. A metal bump is formed over the metal pad structure and the polyimide layer. The polyimide is a reaction product of a dianhydride and a diamine, wherein at least one of the dianhydride and the diamine comprises one selected from the group consisting of a cycloalkane, a fused ring, a bicycloalkane, a tricycloalkane, a bicycloalkene, a tricycloalkene, a spiroalkane, and a heterocyclic ring.

公开(公告)号：US11824026B2

公开(公告)日：2023-11-21

申请号：US17113480

申请日：2020-12-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Shien Chen ,  Sheng-Yu Wu ,  Mirng-Ji Lii ,  Chita Chuang

IPC: H01L23/00

CPC classification number: H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/81 ,  H01L24/94 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/03614 ,  H01L2224/03912 ,  H01L2224/03916 ,  H01L2224/0401 ,  H01L2224/05082 ,  H01L2224/05166 ,  H01L2224/05187 ,  H01L2224/05553 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05684 ,  H01L2224/1132 ,  H01L2224/1144 ,  H01L2224/1145 ,  H01L2224/1147 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11906 ,  H01L2224/131 ,  H01L2224/13007 ,  H01L2224/13013 ,  H01L2224/13021 ,  H01L2224/13082 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/14131 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/8183 ,  H01L2224/81191 ,  H01L2224/81805 ,  H01L2224/81815 ,  H01L2224/81825 ,  H01L2224/94 ,  H01L2224/05187 ,  H01L2924/04953 ,  H01L2224/05166 ,  H01L2924/00014 ,  H01L2224/0345 ,  H01L2924/00014 ,  H01L2224/03452 ,  H01L2924/00014 ,  H01L2224/131 ,  H01L2924/014 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2224/13124 ,  H01L2924/00014 ,  H01L2224/13144 ,  H01L2924/00014 ,  H01L2224/13155 ,  H01L2924/00014 ,  H01L2224/13139 ,  H01L2924/00014 ,  H01L2224/13164 ,  H01L2924/00014 ,  H01L2224/13111 ,  H01L2924/00014 ,  H01L2224/13109 ,  H01L2924/00014 ,  H01L2224/1145 ,  H01L2924/00014 ,  H01L2224/11462 ,  H01L2924/00014 ,  H01L2224/1132 ,  H01L2924/00014 ,  H01L2224/11334 ,  H01L2924/00014 ,  H01L2224/1144 ,  H01L2924/00014 ,  H01L2224/11464 ,  H01L2924/00014 ,  H01L2224/03462 ,  H01L2924/00014 ,  H01L2224/1147 ,  H01L2924/00012 ,  H01L2224/94 ,  H01L2224/03 ,  H01L2224/94 ,  H01L2224/11 ,  H01L2224/05624 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2224/05684 ,  H01L2924/00014 ,  H01L2224/05639 ,  H01L2924/00014 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2224/03464 ,  H01L2924/00014 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2224/81805 ,  H01L2924/00014 ,  H01L2224/81825 ,  H01L2924/00014 ,  H01L2224/8183 ,  H01L2924/00014 ,  H01L2224/05655 ,  H01L2924/00014

Abstract: Connector structures and methods of forming the same are provided. A method includes forming a first patterned passivation layer on a workpiece, the first patterned passivation layer having a first opening exposing a conductive feature of the workpiece. A seed layer is formed over the first patterned passivation layer and in the first opening. A patterned mask layer is formed over the seed layer, the patterned mask layer having a second opening exposing the seed layer, the second opening overlapping with the first opening. A connector is formed in the second opening. The patterned mask layer is partially removed, an unremoved portion of the patterned mask layer remaining in the first opening. The seed layer is patterned using the unremoved portion of the patterned mask layer as a mask.

公开(公告)号：US11791243B2

公开(公告)日：2023-10-17

申请号：US17815515

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chia Hu ,  Sen-Bor Jan ,  Hsien-Wei Chen ,  Ming-Fa Chen

IPC: H01L23/48 ,  H01L23/528 ,  H01L21/768 ,  H01L21/66 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L21/76805 ,  H01L22/32 ,  H01L23/528 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/09 ,  H01L24/80 ,  H01L24/08 ,  H01L2224/03 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/08146 ,  H01L2224/08235 ,  H01L2224/80447 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06596 ,  H01L2924/14 ,  H01L2224/05147 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2224/05124 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2224/05166 ,  H01L2924/00014 ,  H01L2224/05186 ,  H01L2924/04941 ,  H01L2924/00014 ,  H01L2224/05181 ,  H01L2924/00014 ,  H01L2224/05186 ,  H01L2924/04953 ,  H01L2924/00014 ,  H01L2224/80447 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2224/05147 ,  H01L2924/00014

Abstract: A semiconductor device including a test pad contact and a method of manufacturing the semiconductor device are disclosed. In an embodiment, a semiconductor device may include a first metal feature and a second metal feature disposed in a single top metal layer over a substrate. A test pad may be formed over and electrically connected to the first metal feature. A first passivation layer may be formed over the second metal feature and the test pad and may cover top and side surfaces of the test pad. A first via may be formed penetrating the first passivation layer and contacting the test pad and a second via may be formed penetrating the first passivation layer and contacting the second metal feature.