公开(公告)号：US20240079355A1

公开(公告)日：2024-03-07

申请号：US18499527

申请日：2023-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-su LEE ,  Hong Sik CHAE ,  Youn Soo KIM ,  Tae Kyun KIM ,  Youn Joung CHO

IPC: H01L23/64 ,  H10B12/00

CPC classification number: H01L23/642 ,  H10B12/30

Abstract: Provided a semiconductor device comprises, a plurality of semiconductor patterns spaced in a first direction; a plurality of mold insulating layers between the plurality of semiconductor patterns, a plurality of silicide patterns contacting the plurality of semiconductor patterns; and a plurality of first metal conductive films between the plurality of mold insulating layers and connected to each of the silicide patterns, wherein each of the silicide patterns includes a first sidewall that faces the semiconductor pattern, and a second sidewall which faces the first metal conductive film, the first sidewall of the silicide pattern and the second sidewall of the silicide pattern extends in the first direction, and the first sidewall of the silicide pattern and the second sidewall of the silicide pattern are curved surfaces.

公开(公告)号：US20220093532A1

公开(公告)日：2022-03-24

申请号：US17470370

申请日：2021-09-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-su LEE ,  Hong Sik CHAE ,  Youn Soo KIM ,  Tae Kyun KIM ,  Youn Joung CHO

IPC: H01L23/64 ,  H01L27/108

Abstract: Provided a semiconductor device comprises, a plurality of semiconductor patterns spaced in a first direction; a plurality of mold insulating layers between the plurality of semiconductor patterns, a plurality of silicide patterns contacting the plurality of semiconductor patterns; and a plurality of first metal conductive films between the plurality of mold insulating layers and connected to each of the silicide patterns, wherein each of the silicide patterns includes a first sidewall that faces the semiconductor pattern, and a second sidewall which faces the first metal conductive film, the first sidewall of the silicide pattern and the second sidewall of the silicide pattern extends in the first direction, and the first sidewall of the silicide pattern and the second sidewall of the silicide pattern are curved surfaces.

公开(公告)号：US20230260783A1

公开(公告)日：2023-08-17

申请号：US18306463

申请日：2023-04-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-woon PARK ,  Jin-su LEE ,  Hyung-suk JUNG

IPC: H01L21/02 ,  C23C16/04 ,  H01L21/768 ,  H01L21/285

CPC classification number: H01L21/0228 ,  C23C16/045 ,  H01L21/76843 ,  H01L28/91 ,  H01L21/02296 ,  H01L21/02274 ,  H01L21/28556 ,  H01L21/0262

Abstract: A method of manufacturing a semiconductor device includes forming a three-dimensional (3D) structure on a substrate, forming an adsorption control layer to cover an upper portion of the 3D structure, and forming a material layer on the adsorption control layer and on a lower portion of the 3D structure that is not covered by the adsorption control layer, wherein a minimum thickness of the material layer on the adsorption control layer is less than a maximum thickness of the material layer on the lower portion of the 3D structure.

公开(公告)号：US20210225636A1

公开(公告)日：2021-07-22

申请号：US17224365

申请日：2021-04-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-woon PARK ,  Jin-su LEE ,  Hyung-suk JUNG

IPC: H01L21/02 ,  C23C16/04 ,  H01L21/768 ,  H01L49/02 ,  H01L21/285

Abstract: A method of manufacturing a semiconductor device includes forming a three-dimensional (3D) structure on a substrate, forming an adsorption control layer to cover an upper portion of the 3D structure, and forming a material layer on the adsorption control layer and on a lower portion of the 3D structure that is not covered by the adsorption control layer, wherein a minimum thickness of the material layer on the adsorption control layer is less than a maximum thickness of the material layer on the lower portion of the 3D structure.

公开(公告)号：US20210202693A1

公开(公告)日：2021-07-01

申请号：US17200081

申请日：2021-03-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun-goo KANG ,  Sang-yeol KANG ,  Youn-soo KIM ,  Jin-su LEE ,  Hyung-suk JUNG ,  Kyu-ho CHO

IPC: H01L49/02 ,  C23C16/40 ,  C23C16/455 ,  C23C16/56 ,  H01L21/02 ,  H01L21/285 ,  H01L21/321 ,  H01L27/108

Abstract: A method of manufacturing a semiconductor device includes forming a preliminary lower electrode layer on a substrate, the preliminary lower electrode layer including a niobium oxide; converting at least a portion of the preliminary lower electrode layer to a first lower electrode layer comprising a niobium nitride by performing a nitridation process on the preliminary lower electrode layer; forming a dielectric layer on the first lower electrode layer; and forming an upper electrode on the dielectric layer.

公开(公告)号：US20170069711A1

公开(公告)日：2017-03-09

申请号：US15212299

申请日：2016-07-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-su LEE ,  Gihee CHO ,  DONGKYUN PARK ,  Hyun-Suk LEE ,  HEESOOK PARK ,  JONGMYEONG LEE

IPC: H01L49/02

CPC classification number: H01L28/75

Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate and capacitor electrically connected to the substrate. The capacitor includes a lower electrode, a dielectric layer disposed on the lower electrode, and an upper electrode disposed on the dielectric layer. The upper electrode includes a first electrode on the dielectric layer and a second electrode on the first electrode, such that the first electrode is disposed between the dielectric layer and the second electrode. The first electrode contains metal oxynitride having a formula of MxOyNz, in which an atomic ratio (y/x) of oxygen (O) to metallic element (M) is a value in the range from 0.5 to 2.

Abstract translation: 公开了一种半导体器件。 半导体器件包括电连接到衬底的衬底和电容器。 电容器包括下电极，设置在下电极上的电介质层和设置在电介质层上的上电极。 上电极包括介电层上的第一电极和第一电极上的第二电极，使得第一电极设置在电介质层和第二电极之间。 第一电极含有具有式MxOyNz的金属氧氮化物，其中氧（O）与金属元素（M）的原子比（y / x）为0.5至2的值。