SYSTEMS, METHODS, AND APPARATUS FOR SELECTING DEVICES IN TIERED MEMORY

    公开(公告)号:US20230342045A1

    公开(公告)日:2023-10-26

    申请号:US17840587

    申请日:2022-06-14

    CPC classification number: G06F3/0631 G06F3/0604 G06F3/0679

    Abstract: A method may include receiving a request for a memory page in a memory tier comprising a first memory device and a second memory device, wherein the first memory device has a first parameter and the second memory device has a second parameter, selecting, based on the first parameter and the second parameter, the first memory device, and allocating, based on the request, based on the selecting, the memory page from the first memory device. The selecting may include determining a first result based on the first parameter, determining a second result based on the second parameter, and comparing the first result and the second result. The determining the first result may include combining the first parameter with a first weight. The first weight may include a first scale factor, and the combining the first parameter with the first weight may include multiplying the first parameter and the first scale factor.

    TAIL LATENCY AWARE FOREGROUND GARBAGE COLLECTION ALGORITHM

    公开(公告)号:US20180210825A1

    公开(公告)日:2018-07-26

    申请号:US15461467

    申请日:2017-03-16

    Abstract: A Solid State Drive (SSD) is disclosed. The SSD may include a host interface logic to receive a write command from a host and flash memory to store data. The SSD may also include an SSD controller, which may include storage for a just-in-time threshold and a tail latency threshold flash translation layer. The flash translation layer may invoke a just-in-time garbage collection strategy when the number of free pages on the SSD is less than the just-in-time threshold, and a tail latency-aware garbage collection strategy when the number of free pages is less than the tail latency threshold. The tail latency-aware garbage collection strategy may pair the write command with a garbage collection command.

    SYSTEMS, METHODS, AND APPARATUS FOR UPSTREAM PORT DUPLICATION ON VIRTUAL SWITCHES

    公开(公告)号:US20250123983A1

    公开(公告)日:2025-04-17

    申请号:US18791405

    申请日:2024-07-31

    Abstract: An apparatus including a switch may include a first interface configured to communicate with at least one memory device, and a second interface configured to communicate with a first physical connector and a second physical connector, where the switch is configured to communicate with a device using the first physical connector using a memory access protocol. The second interface may be configured to communicate with a second device using the second physical connector using the memory access protocol. The apparatus may further include a second switch including a third interface configured to communicate with the at least one memory device, and a fourth interface configured to communicate with a third physical connector and a fourth physical connector, where the second switch may be configured to communicate with the device using the third physical connector using the memory access protocol.

    SYSTEMS, METHODS, AND APPARATUS FOR CACHE MANAGEMENT IN A MEMORY DEVICE

    公开(公告)号:US20250110873A1

    公开(公告)日:2025-04-03

    申请号:US18749563

    申请日:2024-06-20

    Abstract: A system may include a memory device including memory media and storage media, wherein the memory device is configured to perform one or more operations including sending access information; receiving address information; and populating, from the storage media, the memory media with data using the address information; and a device including one or more circuits, wherein the one or more circuits is configured to perform one or more operations including receiving, from the memory device, the access information; determining, using the access information and application weights, the address information; and sending, to the memory device, the address information. The one or more circuits may be further configured to perform one or more operations including sending, to a training system, trace information; receiving a weight set from the training system, wherein the weight set is based on the trace information; and modifying the application weights based on the weight set.

    DUAL MODE STORAGE DEVICE
    9.
    发明申请

    公开(公告)号:US20230062610A1

    公开(公告)日:2023-03-02

    申请号:US17517659

    申请日:2021-11-02

    Abstract: A system is disclosed. The system may include a processor and a memory coupled to the processor. A storage device may also be coupled to the processor. The storage device may include a first interface and a second interface. The storage device may be configured to extend the memory. A mode switch may select a selected interface of the first interface and the second interface for a command issued by the processor.

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