公开(公告)号：US20130250477A1

公开(公告)日：2013-09-26

申请号：US13761294

申请日：2013-02-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jun-Hee LIM

IPC: H01G4/018 ,  H01G4/01

CPC classification number: H01G4/018 ,  H01G4/01 ,  H01G4/085 ,  H01G4/33 ,  H01G4/38 ,  H01L27/10852 ,  H01L28/91 ,  Y10T29/435

Abstract: A method of forming a capacitor structure includes forming a mold layer on a substrate, in which the substrate includes a plurality of plugs therein, partially removing the mold layer to form a plurality of openings, in which the plugs are exposed by the openings, forming a plurality of lower electrodes filling the openings, in which the lower electrodes have a pillar shape, removing an upper portion of the mold layer to expose upper portions of the lower electrodes, forming a supporting pattern on exposed upper sidewalls of the lower electrodes and on the mold layer, removing the mold layer, and sequentially forming a dielectric layer and an upper electrode on the lower electrodes and the supporting pattern.

Abstract translation: 形成电容器结构的方法包括在基板上形成模具层，其中基板在其中包括多个塞子，部分地移除模具层以形成多个开口，其中插头由开口暴露，形成 填充开口的多个下电极，其中下电极具有柱形，去除模具层的上部以暴露下电极的上部，在下电极的暴露的上侧壁上形成支撑图案，并且在 模具层，去除模具层，并且在下电极和支撑图案上依次形成电介质层和上电极。

公开(公告)号：US20190363014A1

公开(公告)日：2019-11-28

申请号：US16243338

申请日：2019-01-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-Hwan LEE ,  Chang-Seok KANG ,  Yong-Seok KIM ,  Jun-Hee LIM ,  Kohji KANAMORI

IPC: H01L21/768 ,  H01L23/522 ,  H01L21/3213

Abstract: A vertical semiconductor device includes a conductive pattern structure in which insulation patterns and conductive patterns alternately and repeatedly stacked on the substrate. The conductive pattern structure includes an edge portion having a stair-stepped shape. Each of the conductive patterns includes a pad region corresponding to an upper surface of a stair in the edge portion. A pad conductive pattern is disposed to contact a portion of an upper surface of the pad region. A mask pattern is disposed on an upper surface of the pad conductive pattern. A contact plug penetrates the mask pattern to contact the pad conductive pattern.

公开(公告)号：US20150021684A1

公开(公告)日：2015-01-22

申请号：US14254576

申请日：2014-04-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Jin LEE ,  Jun-Hee LIM ,  Kyung-Eun KIM

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/7838 ,  H01L27/10823 ,  H01L27/10876 ,  H01L29/4236 ,  H01L29/66477

Abstract: A semiconductor device and a method of fabricating a semiconductor device, the device including an active region on a substrate, the active region being defined by a field region; gate trenches in the active region of the substrate; gate structures respectively formed in the gate trenches; and at least one carrier barrier layer in the substrate and under the gate trenches.

Abstract translation: 一种半导体器件和制造半导体器件的方法，所述器件包括在衬底上的有源区，所述有源区由场区限定; 在衬底的有源区中的栅极沟槽; 分别形成在栅极沟槽中的栅极结构; 以及衬底中的至少一个载流子阻挡层和栅极沟槽之下。

公开(公告)号：US20150235852A1

公开(公告)日：2015-08-20

申请号：US14535437

申请日：2014-11-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jun-Hee LIM ,  Ki-Jae HUR ,  Sung-Hwan KIM ,  Hae-In JUNG ,  Soo-Jin HONG

IPC: H01L21/265 ,  H01L21/324 ,  H01L29/66 ,  H01L21/306

CPC classification number: H01L21/26506 ,  H01L21/324 ,  H01L29/4236 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/78

Abstract: In a method of manufacturing a semiconductor device, a gate structure is formed on a substrate. An ion implantation process is performed at an upper portion of the substrate exposed by the gate structure, so that an ion implantation region is formed to have an expanded volume. The ion implantation process uses ions that are identical to a material of the substrate.

Abstract translation: 在制造半导体器件的方法中，在衬底上形成栅极结构。 在由栅极结构暴露的衬底的上部进行离子注入工艺，使得形成离子注入区域以具有膨胀的体积。 离子注入工艺使用与衬底材料相同的离子。

公开(公告)号：US20130270672A1

公开(公告)日：2013-10-17

申请号：US13780146

申请日：2013-02-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun-Hee LIM ,  Chan-Seung HWANG

IPC: H01L49/02

CPC classification number: H01L28/60 ,  H01L27/10852 ,  H01L28/91

Abstract: A semiconductor device is provided. The semiconductor device includes first and second storage electrodes formed to be spaced apart from each other on a substrate, an insulating continuous support pattern connected to top surfaces of the first and second storage electrodes, a storage dielectric layer formed to cover the first and second storage electrodes and the continuous support pattern, and a plate electrode formed on the storage dielectric layer. The continuous support pattern includes a first contact part connected to the top surface of the first storage electrode, a second contact part connected to the top surface of the second storage electrode, and a connection part connecting the first and second contact parts with each other.

Abstract translation: 提供半导体器件。 半导体器件包括在基板上形成为彼此间隔开的第一和第二存储电极，连接到第一和第二存储电极的顶表面的绝缘连续支撑图案，形成为覆盖第一和第二存储器 电极和连续支撑图案，以及形成在存储介质层上的平板电极。 连续支撑图案包括连接到第一存储电极的顶表面的第一接触部分，连接到第二存储电极的顶表面的第二接触部分和将第一和第二接触部分彼此连接的连接部分。

公开(公告)号：US20190296047A1

公开(公告)日：2019-09-26

申请号：US16441163

申请日：2019-06-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-il CHANG ,  Jun-Hee LIM ,  Yong-Seok KIM ,  Tae-Young KIM ,  Jae-Sung SIM ,  Su-Jin AHN ,  Ji-Yeong HWANG

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L29/78 ,  H01L29/66 ,  H01L27/11578 ,  H01L21/265 ,  H01L27/11556

Abstract: In a method of manufacturing a vertical semiconductor device, an insulation layer and a sacrificial layer are alternatively and repeatedly formed on a substrate to define a structure. The structure is etched to form a hole therethrough that exposes the substrate. A first semiconductor pattern is formed in a lower portion of the hole, and a blocking pattern, a charge storage pattern, a tunnel insulation pattern and a first channel pattern are formed on a sidewall of the hole. A second channel pattern is formed on the first channel pattern and the semiconductor pattern, and a second semiconductor pattern is formed on a portion of the second channel pattern on the semiconductor pattern to define an upper channel pattern including the second channel pattern and the second semiconductor pattern. The sacrificial layers are replaced with a plurality of gates, respectively, including a conductive material.

公开(公告)号：US20150123238A1

公开(公告)日：2015-05-07

申请号：US14465982

申请日：2014-08-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Ho JANG ,  Dong-Jin LEE ,  Bong-Soo KIM ,  Jun-Hee LIM ,  Joon HAN

IPC: H01L23/485 ,  H01L23/48

CPC classification number: H01L27/108 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10844 ,  H01L27/10855 ,  H01L27/10864 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/12 ,  H01L27/13 ,  H01L29/785

Abstract: There is provided a semiconductor device. The semiconductor device may include multiple contacts plugs, an insulation layer pattern, a metal oxide layer pattern, a metal pattern and a metal line. The contact plugs contact a substrate. The insulation layer pattern is formed between the contact plugs and has a top surface lower than those of the contact plugs. The metal oxide layer pattern is formed on the insulation layer pattern, and has a dielectric constant higher than that of silicon oxide. The metal pattern is formed on the metal oxide layer pattern and contacts sidewalls of the contact plugs. The metal line contacts top surfaces of the contact plugs and the metal pattern and extends thereon.

Abstract translation: 提供了一种半导体器件。 半导体器件可以包括多个触点插头，绝缘层图案，金属氧化物层图案，金属图案和金属线。 接触插头接触基板。 绝缘层图案形成在接触插塞之间，并且具有比接触插塞低的顶表面。 金属氧化物层图案形成在绝缘层图案上，并且具有比氧化硅更高的介电常数。 金属图案形成在金属氧化物层图案上并接触接触插塞的侧壁。 金属线接触接触插塞的顶表面和金属图案并在其上延伸。