公开(公告)号：US20200020396A1

公开(公告)日：2020-01-16

申请号：US16243281

申请日：2019-01-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kohji KANAMORI ,  Chang-Seok KANG ,  Yong-Seok KIM ,  Kyung-Hwan LEE

IPC: G11C13/00 ,  G11C7/12

Abstract: In a method of writing data in a nonvolatile memory device including a plurality of cell strings, each of the plurality of cell strings includes a plurality of memory cells disposed in a vertical direction. A program target page is divided into a plurality of subpages. The program target page is connected to one of a plurality of wordlines. Each of the plurality of subpages includes memory cells that are physically spaced apart from one another. A program operation is sequentially performed on the plurality of subpages. A program verification operation is performed on the program target page including the plurality of subpages at a time.

公开(公告)号：US20190363014A1

公开(公告)日：2019-11-28

申请号：US16243338

申请日：2019-01-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-Hwan LEE ,  Chang-Seok KANG ,  Yong-Seok KIM ,  Jun-Hee LIM ,  Kohji KANAMORI

IPC: H01L21/768 ,  H01L23/522 ,  H01L21/3213

Abstract: A vertical semiconductor device includes a conductive pattern structure in which insulation patterns and conductive patterns alternately and repeatedly stacked on the substrate. The conductive pattern structure includes an edge portion having a stair-stepped shape. Each of the conductive patterns includes a pad region corresponding to an upper surface of a stair in the edge portion. A pad conductive pattern is disposed to contact a portion of an upper surface of the pad region. A mask pattern is disposed on an upper surface of the pad conductive pattern. A contact plug penetrates the mask pattern to contact the pad conductive pattern.

公开(公告)号：US20190148400A1

公开(公告)日：2019-05-16

申请号：US16120364

申请日：2018-09-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min-Yeong SONG ,  Chang-Seok KANG

IPC: H01L27/11582 ,  H01L29/10 ,  H01L29/423 ,  H01L27/1157 ,  H01L21/311 ,  H01L21/768 ,  H01L21/02 ,  H01L21/3065

Abstract: A vertical semiconductor device may include a first gate pattern, second gate patterns, a first channel hole, a first semiconductor pattern, a second channel hole, and a second semiconductor pattern. The first gate pattern may extend in a first direction on a substrate including first and second regions. The first direction may be parallel to an upper surface of the substrate, and a portion of the first gate pattern on the second region may include a first opening. The second gate patterns may be vertically stacked and spaced apart from each other on the first gate pattern, and each of the second gate patterns may extend in the first direction. The first channel hole may extend through the second gate patterns and the first gate pattern and expose a first portion of the substrate on the first region of the substrate. The first semiconductor pattern may be at a lower portion of the first channel hole. The second channel hole may extend through the second gate patterns and expose a second portion of the substrate on the second region of the substrate, and the second channel hole may be disposed within an area of the first opening in a plan view, wherein the first opening has a larger area than the second channel hole in a plan view. The second semiconductor pattern may be at a lower portion of the second channel hole.

公开(公告)号：US20140183615A1

公开(公告)日：2014-07-03

申请号：US14163228

申请日：2014-01-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Hyung Kim ,  Sung-II CHANG ,  Chang-Seok KANG ,  Jung-Dal CHOI

IPC: H01L29/788 ,  H01L29/792

CPC classification number: H01L29/792 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11529 ,  H01L27/11563 ,  H01L27/11568 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/42348 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/788 ,  H01L29/7883

Abstract: A non-volatile memory device may include a semiconductor substrate and an isolation layer on the semiconductor substrate wherein the isolation layer defines an active region of the semiconductor substrate. A tunnel insulation layer may be provided on the active region of the semiconductor substrate, and a charge storage pattern may be provided on the tunnel insulation layer. An interface layer pattern may be provided on the charge storage pattern, and a blocking insulation pattern may be provided on the interface layer pattern. Moreover, the block insulation pattern may include a high-k dielectric material, and the interface layer pattern and the blocking insulation pattern may include different materials. A control gate electrode may be provided on the blocking insulating layer so that the blocking insulation pattern is between the interface layer pattern and the control gate electrode. Related methods are also discussed.

Abstract translation: 非易失性存储器件可以包括半导体衬底和半导体衬底上的隔离层，其中隔离层限定半导体衬底的有源区。 可以在半导体衬底的有源区上设置隧道绝缘层，并且可以在隧道绝缘层上设置电荷存储图案。 可以在电荷存储图案上提供界面层图案，并且可以在界面层图案上提供阻挡绝缘图案。 此外，块绝缘图案可以包括高k介电材料，并且界面层图案和阻挡绝缘图案可以包括不同的材料。 可以在阻挡绝缘层上设置控制栅电极，使得阻挡绝缘图案位于界面层图案和控制栅电极之间。 还讨论了相关方法。