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公开(公告)号：US11776644B2
公开(公告)日：2023-10-03
申请号：US17591987
申请日：2022-02-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Minho Choi , Jaeseong Lim , Kyungryun Kim , Daehyun Kim , Wonil Bae , Hohyun Shin , Sanghoon Jung , Hyongryol Hwang
Abstract: A voltage trimming circuit including: a first resistance circuit having a first resistance value determined by up codes and down codes; a second resistance circuit having a second resistance value determined by the up codes and the down codes; and a comparator to output a voltage detection signal by comparing a voltage level of a reference voltage trimming node to that of a feedback node, wherein the voltage detection signal adjusts the up and down codes, which increase the first resistance value and decrease the second resistance value when the voltage level of the reference voltage trimming node is higher than that of the feedback node, and adjusts the up and down codes, which decrease the first resistance value and increase the second resistance value when the voltage level of the reference voltage trimming node is lower than that of the feedback node.
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2.发明申请公开(公告)号：US20250140332A1
公开(公告)日：2025-05-01
申请号：US18799907
申请日：2024-08-09
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Changyoung Lee , Sanghoon Jung , Changsik Yoo
Abstract: An example memory device includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer includes a memory cell array, a first bonding pad, and a first test pad. The second semiconductor layer is disposed with respect to the first semiconductor layer in a vertical direction, and includes a peripheral circuit, a second bonding pad connected to the first bonding pad, a second test pad connected to the first test pad, and a test circuit. The test circuit checks a connection state of the first and second bonding pads. The test circuit receives a first test signal through the first and second test pads, generates a first test result signal representing a first misalignment between the first and second bonding pads based on the first test signal, and compensates an operation of the peripheral circuit based on the first test result signal.
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公开(公告)号：US12100635B2
公开(公告)日：2024-09-24
申请号：US17185116
申请日：2021-02-25
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sanghoon Jung , Young Lyong Kim , Cheolsoo Han
CPC classification number: H01L23/3157 , H01L21/563 , H01L23/49833 , H01L23/49838 , H01L24/32 , H01L24/83 , H01L25/18 , H01L23/481 , H01L23/49816 , H01L23/49822 , H01L24/92 , H01L2224/32054 , H01L2224/32057 , H01L2224/32225 , H01L2224/83939 , H01L2224/92125
Abstract: Disclosed is a semiconductor package comprising a lower substrate including a conductive line; a first semiconductor chip on the lower substrate; an under-fill layer between the first semiconductor chip and the lower substrate, the under-fill layer including a central part below the first semiconductor chip and an edge part isolated from direct contact with the central part in a first direction parallel to a top surface of the lower substrate, and a recess region between the central part and the edge part. The recess region may be defined by a sidewall of the central part, a sidewall of the edge part, and a top surface of the conductive line in the lower substrate.
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公开(公告)号：US12062404B2
公开(公告)日：2024-08-13
申请号：US18239548
申请日：2023-08-29
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Minho Choi , Jaeseong Lim , Kyungryun Kim , Daehyun Kim , Wonil Bae , Hohyun Shin , Sanghoon Jung , Hyongryol Hwang
Abstract: A voltage trimming circuit including: a first resistance circuit having a first resistance value determined by up codes and down codes; a second resistance circuit having a second resistance value determined by the up codes and the down codes; and a comparator to output a voltage detection signal by comparing a voltage level of a reference voltage trimming node to that of a feedback node, wherein the voltage detection signal adjusts the up and down codes, which increase the first resistance value and decrease the second resistance value when the voltage level of the reference voltage trimming node is higher than that of the feedback node, and adjusts the up and down codes, which decrease the first resistance value and increase the second resistance value when the voltage level of the reference voltage trimming node is lower than that of the feedback node.
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公开(公告)号：US20250126810A1
公开(公告)日：2025-04-17
申请号：US18734650
申请日：2024-06-05
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Changyoung LEE , Sanghoon Jung , Youngseok Park , Changsik Yoo
IPC: H10B80/00 , H01L23/00 , H01L25/065 , H01L25/18 , H10B12/00
Abstract: A memory device is provided. The memory device includes: a plurality of sub-array regions arranged spaced apart in a first and second horizontal directions, and each sub-array region including a plurality of memory cells, the first horizontal direction crossing the second horizontal direction; a dummy region disposed between the plurality of sub-array regions, the dummy region including a first metal pattern extending in the first horizontal direction at a first layer, a first lower contact extending in a vertical direction on a first portion of the first metal pattern, and a second lower contact extending in the vertical direction on a second portion of the first metal pattern; and a peripheral circuit region including a first upper contact connected to the first lower contact, a first circuit connected to the first upper contact, a second upper contact connected to the second lower contact, and a second circuit connected to the second upper contact.
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Patent Agency Ranking
公开(公告)号：US20250166693A1
公开(公告)日：2025-05-22
申请号：US18781150
申请日：2024-07-23
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sanghoon Jung , Changyoung Lee , Jeongdon Ihm
IPC: G11C11/408 , H01L23/00 , H03K19/20
Abstract: A memory device includes a row decoder connected to a plurality of word lines of each of a plurality of memory blocks. The row decoder includes a main word line driver circuit commonly connected to the plurality of memory blocks and configured to generate first main word line driving signals, second main word line driving signals, and sub-word line driving signals based on row address signals, and a sub-word line driving signal connected to each of the plurality of memory blocks and configured to activate one word line from among the plurality of word lines using a NOR logic circuit to which the first main word line driving signals, the second main word line driving signals, and the sub-word line driving signals are connected.
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公开(公告)号：US12262496B2
公开(公告)日：2025-03-25
申请号：US17974002
申请日：2022-10-26
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sukchul Park , Beommo Seong , Sanghoon Jung , Woonbae Kim , Jinsu Park , Byounguk Yoon
IPC: H05K5/00 , H04B1/3818 , H05K5/02
Abstract: An electronic device includes a circuit board, a socket on the circuit board and electrically connected to the circuit board, and a tray removably insertable into the socket from outside the electronic device, the tray including a body portion, a first protrusion extended from the body portion, and a second protrusion extended from the body and spaced apart from the first protrusion. The socket includes a detection portion which is engageable with the first protrusion of the tray and detects insertion of the tray in the socket, together with the circuit board, and a supporting portion which is engageable with the second protrusion of the tray. The tray which is inserted into the socket disposes the first protrusion contacting the detection portion, and a portion of the tray corresponding to the second protrusion supported by the supporting portion.
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公开(公告)号：US20230410925A1
公开(公告)日：2023-12-21
申请号：US18239548
申请日：2023-08-29
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Minho Choi , Jaeseong Lim , Kyungryun Kim , Daehyun Kim , Wonil Bae , Hohyun Shin , Sanghoon Jung , Hyongryol Hwang
Abstract: A voltage trimming circuit including: a first resistance circuit having a first resistance value determined by up codes and down codes; a second resistance circuit having a second resistance value determined by the up codes and the down codes; and a comparator to output a voltage detection signal by comparing a voltage level of a reference voltage trimming node to that of a feedback node, wherein the voltage detection signal adjusts the up and down codes, which increase the first resistance value and decrease the second resistance value when the voltage level of the reference voltage trimming node is higher than that of the feedback node, and adjusts the up and down codes, which decrease the first resistance value and increase the second resistance value when the voltage level of the reference voltage trimming node is lower than that of the feedback node.
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公开(公告)号：US20220284975A1
公开(公告)日：2022-09-08
申请号：US17591987
申请日：2022-02-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Minho Choi , Jaeseong Lim , Kyungryun Kim , Daehyun Kim , Wonil Bae , Hohyun Shin , Sanghoon Jung , Hyongryol Hwang
Abstract: A voltage trimming circuit including: a first resistance circuit having a first resistance value determined by up codes and down codes; a second resistance circuit having a second resistance value determined by the up codes and the down codes; and a comparator to output a voltage detection signal by comparing a voltage level of a reference voltage trimming node to that of a feedback node, wherein the voltage detection signal adjusts the up and down codes, which increase the first resistance value and decrease the second resistance value when the voltage level of the reference voltage trimming node is higher than that of the feedback node, and adjusts the up and down codes, which decrease the first resistance value and increase the second resistance value when the voltage level of the reference voltage trimming node is lower than that of the feedback node.
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公开(公告)号：US11257537B2
公开(公告)日：2022-02-22
申请号：US17034058
申请日：2020-09-28
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sanghoon Jung
IPC: G11C5/14 , G11C11/4074 , G11C11/4091 , G11C11/4094
Abstract: Provided are a voltage generator circuitry for generating an internal power supply voltage of a memory device and an operation method thereof. In the memory device, a voltage generator circuitry generates a first internal power supply voltage when the memory device is in an active mode, generates a second internal power supply voltage when the memory device is in a standby mode, and provides the first internal power supply voltage or the second internal power supply voltage to an internal power supply voltage line for using as an internal power supply voltage of the memory device. When the memory device is in the standby mode, the voltage generator circuitry blocks generation of the first internal power supply voltage by using a first voltage higher than an external power supply voltage.
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