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公开(公告)号：US12073910B2
公开(公告)日：2024-08-27
申请号：US18169769
申请日：2023-02-15
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jongcheol Kim , Hyunsung Shin , Hohyun Shin , Taeyoung Oh , Kyungsoo Ha
IPC: G11C7/10 , G06F3/06 , G11C11/4093 , G11C11/4096 , G06F11/10 , G11C11/408
CPC classification number: G11C7/1012 , G06F3/0619 , G11C11/4093 , G11C11/4096 , G06F3/0659 , G06F3/0679 , G06F11/1068 , G11C11/4082 , G11C2207/005
Abstract: A semiconductor memory device includes a memory cell array, a data input/output (I/O) buffer, an I/O gating circuit and a control logic circuit. The memory cell array includes a plurality of sub array blocks arranged in a first direction and a second direction. The data I/O buffer exchanges user data with a memory controller through I/O pads. The I/O gating circuit is connected to the data I/O buffer through data buses and connected to the memory cell array through data I/O lines, and programs mapping relationship between the sub array blocks and the I/O pads, based on a mapping control signal such that uncorrectable errors that are detected by an error correction code engine in the memory controller are reduced. The control logic circuit generates the mapping control signal based on identifier information indicating a type of a central processing unit of the memory controller.
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公开(公告)号：US11776644B2
公开(公告)日：2023-10-03
申请号：US17591987
申请日：2022-02-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Minho Choi , Jaeseong Lim , Kyungryun Kim , Daehyun Kim , Wonil Bae , Hohyun Shin , Sanghoon Jung , Hyongryol Hwang
Abstract: A voltage trimming circuit including: a first resistance circuit having a first resistance value determined by up codes and down codes; a second resistance circuit having a second resistance value determined by the up codes and the down codes; and a comparator to output a voltage detection signal by comparing a voltage level of a reference voltage trimming node to that of a feedback node, wherein the voltage detection signal adjusts the up and down codes, which increase the first resistance value and decrease the second resistance value when the voltage level of the reference voltage trimming node is higher than that of the feedback node, and adjusts the up and down codes, which decrease the first resistance value and increase the second resistance value when the voltage level of the reference voltage trimming node is lower than that of the feedback node.
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公开(公告)号：US11094390B2
公开(公告)日：2021-08-17
申请号：US16795730
申请日：2020-02-20
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kyungryun Kim , Yoonna Oh , Hohyun Shin , Jaeho Lee
Abstract: A semiconductor memory device comprises a memory cell array including segments disposed at corresponding intersections of row and column blocks, each row block including dynamic memory cells coupled to word-lines and bit-lines, a row decoder that activates a first word-line of a first row block in response to a row address, determines whether the first row block is a master block based on a first fuse information and a second row block is mapped as a slave to the master block, activates a second word-line of the second row block, and outputs a row block information signal, and a column decoder accessing a portion of first memory cells coupled to the first word-line or a portion of second memory cells coupled to the second word-line based on a column address, the row block information signal and a second fuse information.
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公开(公告)号：US20240371417A1
公开(公告)日：2024-11-07
申请号：US18771859
申请日：2024-07-12
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jongcheol Kim , Hyunsung Shin , Hohyun Shin , Taeyoung Oh , Kyungsoo Ha
IPC: G11C7/10 , G06F3/06 , G06F11/10 , G11C11/408 , G11C11/4093 , G11C11/4096
Abstract: A semiconductor memory device includes a memory cell array, a data input/output (I/O) buffer, an I/O gating circuit and a control logic circuit. The memory cell array includes a plurality of sub array blocks arranged in a first direction and a second direction. The data VO buffer exchanges user data with a memory controller through I/O pads. The I/O gating circuit is connected to the data I/O buffer through data buses and connected to the memory cell array through data I/O lines, and programs mapping relationship between the sub array blocks and the I/O pads, based on a mapping control signal such that uncorrectable errors that are detected by an error correction code engine in the memory controller are reduced. The control logic circuit generates the mapping control signal based on identifier information indicating a type of a central processing unit of the memory controller.
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公开(公告)号：US11334457B1
公开(公告)日：2022-05-17
申请号：US16839675
申请日：2020-04-03
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hohyun Shin , Jongwan Kim , Hyungi Kim , Hyunsung Shin , Dongmin Kim , Myeongo Kim , Kwangil Park , Youngsoo Sohn
Abstract: A semiconductor memory device including a memory cell array and an error relief circuit may be provided. The memory cell array includes plurality of memory cells which store data and are coupled to a plurality of word-lines and a plurality of bit-lines. The error relief circuit includes a replacement memory. The error relief circuit receives a command and an address from an external device, stores a first data associated with a first address in the replacement memory in response to detecting a sequence of the consecutively received commands with respect to the first address, and inputs/outputs the first data associated with the first address through the replacement memory.
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Patent Agency Ranking
公开(公告)号：US12062404B2
公开(公告)日：2024-08-13
申请号：US18239548
申请日：2023-08-29
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Minho Choi , Jaeseong Lim , Kyungryun Kim , Daehyun Kim , Wonil Bae , Hohyun Shin , Sanghoon Jung , Hyongryol Hwang
Abstract: A voltage trimming circuit including: a first resistance circuit having a first resistance value determined by up codes and down codes; a second resistance circuit having a second resistance value determined by the up codes and the down codes; and a comparator to output a voltage detection signal by comparing a voltage level of a reference voltage trimming node to that of a feedback node, wherein the voltage detection signal adjusts the up and down codes, which increase the first resistance value and decrease the second resistance value when the voltage level of the reference voltage trimming node is higher than that of the feedback node, and adjusts the up and down codes, which decrease the first resistance value and increase the second resistance value when the voltage level of the reference voltage trimming node is lower than that of the feedback node.
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公开(公告)号：US20240012712A1
公开(公告)日：2024-01-11
申请号：US18169769
申请日：2023-02-15
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jongcheol Kim , Hyunsung Shin , Hohyun Shin , Taeyoung Oh , Kyungsoo Ha
IPC: G06F11/10 , G06F3/06 , G11C11/4096 , G11C11/408
CPC classification number: G06F11/1068 , G06F3/0619 , G06F3/0659 , G06F3/0679 , G11C11/4096 , G11C11/4082
Abstract: A semiconductor memory device includes a memory cell array, a data input/output (I/O) buffer, an I/O gating circuit and a control logic circuit. The memory cell array includes a plurality of sub array blocks arranged in a first direction and a second direction. The data I/O buffer exchanges user data with a memory controller through I/O pads. The I/O gating circuit is connected to the data I/O buffer through data buses and connected to the memory cell array through data I/O lines, and programs mapping relationship between the sub array blocks and the I/O pads, based on a mapping control signal such that uncorrectable errors that are detected by an error correction code engine in the memory controller are reduced. The control logic circuit generates the mapping control signal based on identifier information indicating a type of a central processing unit of the memory controller.
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公开(公告)号：US20230410925A1
公开(公告)日：2023-12-21
申请号：US18239548
申请日：2023-08-29
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Minho Choi , Jaeseong Lim , Kyungryun Kim , Daehyun Kim , Wonil Bae , Hohyun Shin , Sanghoon Jung , Hyongryol Hwang
Abstract: A voltage trimming circuit including: a first resistance circuit having a first resistance value determined by up codes and down codes; a second resistance circuit having a second resistance value determined by the up codes and the down codes; and a comparator to output a voltage detection signal by comparing a voltage level of a reference voltage trimming node to that of a feedback node, wherein the voltage detection signal adjusts the up and down codes, which increase the first resistance value and decrease the second resistance value when the voltage level of the reference voltage trimming node is higher than that of the feedback node, and adjusts the up and down codes, which decrease the first resistance value and increase the second resistance value when the voltage level of the reference voltage trimming node is lower than that of the feedback node.
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公开(公告)号：US11450396B2
公开(公告)日：2022-09-20
申请号：US17398434
申请日：2021-08-10
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kyungryun Kim , Yoonna Oh , Hohyun Shin , Jaeho Lee
Abstract: A semiconductor memory device comprises a memory cell array including segments disposed at corresponding intersections of row and column blocks, each row block including dynamic memory cells coupled to word-lines and bit-lines, a row decoder that activates a first word-line of a first row block in response to a row address, determines whether the first row block is a master block based on a first fuse information and a second row block is mapped as a slave to the master block, activates a second word-line of the second row block, and outputs a row block information signal, and a column decoder accessing a portion of first memory cells coupled to the first word-line or a portion of second memory cells coupled to the second word-line based on a column address, the row block information signal and a second fuse information.
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公开(公告)号：US20220284975A1
公开(公告)日：2022-09-08
申请号：US17591987
申请日：2022-02-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Minho Choi , Jaeseong Lim , Kyungryun Kim , Daehyun Kim , Wonil Bae , Hohyun Shin , Sanghoon Jung , Hyongryol Hwang
Abstract: A voltage trimming circuit including: a first resistance circuit having a first resistance value determined by up codes and down codes; a second resistance circuit having a second resistance value determined by the up codes and the down codes; and a comparator to output a voltage detection signal by comparing a voltage level of a reference voltage trimming node to that of a feedback node, wherein the voltage detection signal adjusts the up and down codes, which increase the first resistance value and decrease the second resistance value when the voltage level of the reference voltage trimming node is higher than that of the feedback node, and adjusts the up and down codes, which decrease the first resistance value and increase the second resistance value when the voltage level of the reference voltage trimming node is lower than that of the feedback node.
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