公开(公告)号：US20180240805A1

公开(公告)日：2018-08-23

申请号：US15956851

申请日：2018-04-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seok-Jung YUN ,  Joon-Hee LEE ,  Seong-Soon CHO

IPC: H01L27/11551 ,  H01L29/792 ,  H01L29/788 ,  H01L29/78 ,  H01L49/02 ,  H01L27/105 ,  H01L27/11582 ,  H01L27/11578 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11597

CPC classification number: H01L21/8221 ,  H01L21/28282 ,  H01L21/76816 ,  H01L21/76832 ,  H01L21/76877 ,  H01L21/823475 ,  H01L27/1052 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/11597 ,  H01L28/00 ,  H01L29/7827 ,  H01L29/7889 ,  H01L29/7926

Abstract: A vertical memory device may include a plurality of word lines spaced apart in a first direction, each extending in a second direction perpendicular to the first direction and having a first width in a third direction perpendicular to the first and second directions, a dummy word line over an uppermost word line, including an opening and having a portion thereof with the first width in the third direction, a first string selection line (SSL) and a second string selection line (SSL) over the dummy word line, the first and second SSLs being at substantially the same level along the first direction, each of the first and second SSLs having a second width less than the first width in the third direction, and a plurality of vertical channel structures, each through the word lines, the dummy word line, and one of the first and second SSLs.

公开(公告)号：US20170040254A1

公开(公告)日：2017-02-09

申请号：US15331224

申请日：2016-10-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Min HWANG ,  Young-Ho LEE ,  Seong-Soon CHO ,  Woon-Kyung LEE

IPC: H01L23/528 ,  H01L27/115

Abstract: Step shape pad structure and wiring structure in vertical type semiconductor device are include a first conductive line having a first line shape and including first pad regions at an upper surface of an edge portion, and a second conductive line having s second line shape and being spaced apart from the first conductive line and provided on the first conductive line. An end portion of the first conductive line is extended to a first position. Second pad regions are included on an upper surface of an edge portion of the second conductive line. An end portion of the second conductive line is extended to the first position. The second conductive line includes a dent portion at a facing portion to the first pad regions in a vertical direction to expose the first pad regions. The pad structure may be used in a vertical type nonvolatile memory device.

Abstract translation: 垂直型半导体器件中的阶形形状焊盘结构和布线结构包括具有第一线形状并且在边缘部分的上表面处包括第一焊盘区域的第一导电线和具有第二线形并且间隔开的第二导线 并且设置在第一导线上。 第一导线的端部延伸到第一位置。 第二焊盘区域包括在第二导线的边缘部分的上表面上。 第二导线的端部延伸到第一位置。 第二导线包括在垂直方向上与第一焊盘区域相对的部分处的凹部，以露出第一焊盘区域。 衬垫结构可以用在垂直型非易失性存储器件中。

公开(公告)号：US20140138759A1

公开(公告)日：2014-05-22

申请号：US14149884

申请日：2014-01-08

Applicant: SAMSUNG Electronics Co., Ltd.

Inventor： Young-Ho LEE ,  Keon-Soo KIM ,  Seong-Soon CHO ,  Jin- Hyun SHIN

IPC: H01L27/06

CPC classification number: H01L27/0629 ,  H01L27/11531 ,  H01L28/20

Abstract: In an integrated circuit device and method of manufacturing the same, a resistor pattern is positioned on a device isolation layer of a substrate. The resistor pattern includes a resistor body positioned in a recess portion of the device isolation layer and a connector making contact with the resistor body and positioned on the device isolation layer around the recess portion. The connector has a metal silicide pattern having electric resistance lower than that of the resistor body at an upper portion. A gate pattern is positioned on the active region of the substrate and includes the metal silicide pattern at an upper portion. A resistor interconnection is provided to make contact with the connector of the resistor pattern. A contact resistance between the connector and the resistor interconnection is reduced.

Abstract translation: 在集成电路器件及其制造方法中，电阻器图案位于衬底的器件隔离层上。 电阻器图案包括位于器件隔离层的凹部中的电阻体，以及与电阻体接触并连接在凹部的周围的器件隔离层上的连接器。 连接器具有在上部具有低于电阻体的电阻的金属硅化物图案。 栅极图案位于衬底的有源区上，并且在上部包括金属硅化物图案。 提供电阻器互连以与电阻器图案的连接器接触。 连接器和电阻器互连之间的接触电阻降低。