公开(公告)号：US09064582B2

公开(公告)日：2015-06-23

申请号：US14316023

申请日：2014-06-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngsun Song ,  Bogeun Kim ,  Ohsuk Kwon ,  Kitae Park ,  Seung-Hwan Shin ,  Sangyong Yoon

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/34 ,  G11C11/56 ,  G11C16/08

CPC classification number: G11C16/10 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/08 ,  G11C16/34 ,  G11C16/3459

Abstract: A nonvolatile memory device includes a memory cell array, a page buffer unit which output a verify-read result, a reference current generating unit which generates a reference current signal, a page buffer decoding unit which outputs currents according to the verify-read result. The nonvolatile memory device further includes an analog bit counting unit which counts the currents, a digital adding unit which calculates an accumulated sum of the counting result, a pass/fail checking unit which outputs a pass signal or fail signal according to the calculation result, and a control unit controlling a program operation.

Abstract translation: 非易失性存储器件包括存储单元阵列，输出验证读取结果的页面缓冲器单元，产生参考电流信号的参考电流产生单元，根据验证读取结果输出电流的页面缓冲器解码单元。 非易失性存储装置还包括对电流进行计数的模拟比特计数单元，计算计数结果的累积和的数字加法单元，根据计算结果输出通过信号或失败信号的通过/失败检查单元， 以及控制程序操作的控制单元。

公开(公告)号：US08958251B2

公开(公告)日：2015-02-17

申请号：US13913710

申请日：2013-06-10

Applicant: Samsung Electronics Co., Ltd

Inventor： Ohsuk Kwon ,  Sang-Hyun Joo ,  HyeongJun Kim ,  Kitae Park ,  Seung-Hwan Shin

IPC: G11C16/06 ,  G11C16/10 ,  G11C16/24 ,  G11C16/34

CPC classification number: G11C16/10 ,  G11C16/24 ,  G11C16/3459

Abstract: A nonvolatile memory device includes a memory cell array including a plurality of memory cells, a page buffer circuit connected with the memory cell array via a plurality of bit lines and configured to selectively pre-charge the plurality of bit lines, and control logic configured to control the page buffer circuit such that a pre-charge voltage is applied to selected bit lines of the plurality of bit lines during a first time at a read operation and such that a pre-charge voltage is applied to selected bit lines of the plurality of bit lines during a second time different from the first time at a verification read operation. The second time is determined on the basis of the number of selected bit lines of the plurality of bit lines at the verification read operation.

Abstract translation: 非易失性存储器件包括包括多个存储器单元的存储单元阵列，经由多个位线与存储单元阵列连接并被配置为选择性地预充电多个位线的页缓冲器电路，以及配置为 控制页面缓冲器电路，使得在读取操作的第一时间期间将预充电电压施加到多个位线的选定位线，并且使得预充电电压被施加到多个位线中的选定位线 在第二时间不同于在验证读取操作的第一时间的位线。 基于在验证读取操作中的多个位线的选定位线的数量来确定第二次。

公开(公告)号：US08867275B2

公开(公告)日：2014-10-21

申请号：US13625114

申请日：2012-09-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-Hwan Shin ,  Kitae Park ,  Hyun-Wook Park ,  Jun-Hee Lee

IPC: G11C16/06 ,  G11C11/56 ,  G11C16/10

CPC classification number: G11C16/10 ,  G11C11/5621 ,  G11C16/06

Abstract: Disclosed is a flash memory device and programming method that includes; receiving buffer data and determining between a high-speed mode and a reliability mode for buffer data, and upon determining the reliability mode storing the buffer data in a first buffer region, and upon determining the high-speed mode storing the buffer data in a second buffer region. The memory cell array of the flash memory including a main region and a separately designated buffer region divided into the first buffer region and second buffer region.

Abstract translation: 公开了一种闪速存储器件和编程方法，包括： 接收缓冲器数据，并在缓冲器数据的高速模式和可靠性模式之间确定，并且在确定将缓冲器数据存储在第一缓冲区域中的可靠性模式时，并且在确定将第二缓冲器数据存储在第二缓冲器数据中的高速模式 缓冲区。 闪速存储器的存储单元阵列包括分为第一缓冲区域和第二缓冲区域的主区域和单独指定的缓冲区域。