公开(公告)号：US10424649B2

公开(公告)日：2019-09-24

申请号：US16026097

申请日：2018-07-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joon-Seok Moon ,  Dong Sik Kong ,  Sung Won Yoo ,  Hee Sun Joo ,  Kyo-Suk Chae

IPC: H01L29/51 ,  H01L29/423 ,  H01L29/78 ,  H01L27/108

Abstract: A semiconductor device includes a substrate, device isolation film defining an active region of the substrate in which a gate trench extends, a gate insulating film disposed along sides and a bottom of the gate trench, a gate electrode disposed on the gate insulating film in the gate trench and having a first portion, a second portion on the first portion, and a third portion on the second portion, a first barrier film pattern interposed between the first portion of the gate electrode and the gate insulating film, a second barrier film pattern interposed between the second portion of the gate electrode and the gate insulating film, and a third barrier film pattern interposed between the third portion of the gate electrode and the gate insulating film. The work function of the first barrier film pattern is greater than the work function of the second barrier film pattern and less than the work function of the third barrier film pattern.

公开(公告)号：US12048150B2

公开(公告)日：2024-07-23

申请号：US17377848

申请日：2021-07-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung Hwan Lee ,  Yong Seok Kim ,  Il Gweon Kim ,  Hyun Cheol Kim ,  Hyeoung Won Seo ,  Sung Won Yoo ,  Jae Ho Hong

IPC: H10B43/20 ,  H10B43/10

CPC classification number: H10B43/20 ,  H10B43/10

Abstract: A semiconductor memory device having improved electrical characteristics is provided. The semiconductor memory device comprises a first semiconductor pattern separated from a substrate in a first direction, a first gate structure extending in the first direction and penetrating the first semiconductor pattern, a first conductive connecting line connected to the first semiconductor pattern and extending in a second direction different from the first direction, and a second conductive connecting line connected to the first semiconductor pattern. The first gate structure is between the first conductive connecting line and the second conductive connecting line, the first gate structure includes a first gate electrode and a first gate insulating film, and the first gate insulating film includes a first charge holding film contacting with the first semiconductor pattern.

公开(公告)号：US11711918B2

公开(公告)日：2023-07-25

申请号：US17227793

申请日：2021-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung Hwan Lee ,  Yong Seok Kim ,  Hyun Cheol Kim ,  Satoru Yamada ,  Sung Won Yoo ,  Jae Ho Hong

IPC: H10B41/70 ,  H10B41/20 ,  H10B41/35 ,  H10B41/41 ,  H10B41/50

CPC classification number: H10B41/70 ,  H10B41/20 ,  H10B41/35 ,  H10B41/41 ,  H10B41/50

Abstract: Provided is a semiconductor memory device. The semiconductor memory device comprises a first semiconductor pattern including a first impurity region, a second impurity region, and a channel region, the first impurity region spaced apart from a substrate in a first direction and having a first conductivity type, the second impurity region having a second conductivity type different from the first conductivity type, and the channel region between the first impurity region and the second impurity region, a first conductive connection line connected to the first impurity region and extending in a second direction different from the first direction and a first gate structure extending in the first direction and including a first gate electrode and a first gate insulating film, wherein the first gate electrode penetrates the channel region and the first gate insulating film is between the first gate electrode and the semiconductor pattern.