公开(公告)号：US12087554B2

公开(公告)日：2024-09-10

申请号：US16905018

申请日：2020-06-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungyeon Kim ,  Jungpyo Hong ,  Kwangnam Kim ,  Hyungjun Kim ,  Jongwoo Sun

IPC: H01J37/32 ,  H01L21/67

CPC classification number: H01J37/32495 ,  H01J37/3211 ,  H01J37/32119 ,  H01J37/3244 ,  H01J37/32715 ,  H01J37/32743 ,  H01L21/67069 ,  H01J2237/334

Abstract: A substrate treating apparatus, including a process chamber having a bottom portion configured to secure a substrate while a substrate treating process is performed on the substrate; and a dielectric window arranged at an upper portion of the process chamber to define a process space, and including: an insulative body, an antenna disposed on an upper surface of the insulative body, a protection layer disposed on a lower surface of the insulative body, and an etch resistor protruding from at least a portion of the protection layer toward the process space, wherein, based on power being applied to the antenna, a plasma is generated in the process space, and wherein the insulative body is protected from the plasma by the protection layer and the etch resistor.

公开(公告)号：US11430679B2

公开(公告)日：2022-08-30

申请号：US16821415

申请日：2020-03-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwangnam Kim ,  Nohsung Kwak ,  Sungyeon Kim ,  Hyungjun Kim ,  Haejoong Park ,  Jongwoo Sun ,  Sangrok Oh ,  Ilyoung Han ,  Jungpyo Hong

IPC: H01L21/67 ,  H01L21/687 ,  H01L21/677 ,  H01L21/673

Abstract: A semiconductor manufacturing apparatus including at least one load module including a load port on which a substrate container is located, a plurality of substrates being mountable on the substrate container; at least one loadlock module including a loadlock chamber directly connected to the substrate container, the loadlock chamber interchangeably having atmospheric pressure and vacuum pressure, a first transfer robot within the loadlock chamber, and a substrate stage within the loadlock chamber, the plurality of substrates being mountable on the substrate stage; a transfer module including a transfer chamber connected to the loadlock chamber, a second transfer robot within the transfer chamber, and a substrate aligner within the transfer chamber; and at least one process module including at least one process chamber connected to the transfer module.

公开(公告)号：US11777860B2

公开(公告)日：2023-10-03

申请号：US17501470

申请日：2021-10-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byeongjo Park ,  Sungyeon Kim ,  Kukjin Kim ,  Sungjun Park ,  Jeongbae Seo ,  Byungho An

IPC: H04L47/2416 ,  H04L43/16 ,  H04L47/32 ,  H04L1/1867

CPC classification number: H04L47/2416 ,  H04L1/1874 ,  H04L43/16 ,  H04L47/32

Abstract: An electronic device includes a NACK buffer configured to temporarily store first packets and second packets, and processing circuitry configured to generate a plurality of frames, which include reference frames depending on decoding of another frame and non-reference frames independent of decoding of another frame, based on hierarchical predictive (P) coding, generate the first packets forming the reference frames and the second packets forming the non-reference frames, based on the plurality of frames, transmit the first packets and the second packets to an external device, receive a NACK request indicating retransmission target packets that have failed to be received by the external device, determine to not retransmit at least some of the retransmission target packets corresponding to the NACK request.

公开(公告)号：US09812335B2

公开(公告)日：2017-11-07

申请号：US15066492

申请日：2016-03-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Je-Woo Han ,  Junho Yoon ,  Kyohyeok Kim ,  Dongchan Kim ,  Sungyeon Kim ,  Jaehong Park ,  Jinyoung Park ,  KyungYub Jeon

IPC: H01L21/311 ,  H01L21/768

CPC classification number: H01L21/31144 ,  H01L21/31116 ,  H01L21/76816

Abstract: A method of fabricating a semiconductor device is disclosed. The method may include forming an target layer on a substrate, forming a mask pattern on a target layer, performing a first process to etch the target layer and form a first sub-trench, and performing a second process to further etch the target layer and form a second sub-trench. First and second sidewall patterns may be formed on a sidewall of the mask pattern to be used as an etch mask in the first and second processes, respectively. Outer sidewalls of the first and second sidewall patterns may be formed to have different angles with respect to a top surface of the substrate.