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公开(公告)号：US20250048643A1
公开(公告)日：2025-02-06
申请号：US18588712
申请日：2024-02-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Suseong Noh , Sangwoo Han , Kwang-Soo Kim , Ilho Myeong
Abstract: The present disclosure relates to a semiconductor device and a data storage system including the device. The semiconductor device has a substrate including a cell array region and a contact region. In the cell array region the semiconductor device has a first horizontal conductive layer, a gate stacking structure including a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked on the substrate. A channel structure extends in a direction crossing into the substrate by penetrating the gate stacking structure in the cell array region, and includes a channel layer connected to the substrate. Surrounding the channel layer is a ferroelectric layer. The first horizontal conductive layer is not in direct contact with the channel layer due to a dummy pattern positioned on the first horizontal conductive layer and disposed between the substrate and the ferroelectric layer.
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公开(公告)号：US20250095759A1
公开(公告)日：2025-03-20
申请号：US18796585
申请日：2024-08-07
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Ilho Myeong , Kwangsoo Kim , Suseong Noh
Abstract: A method of operating a memory device, the method including: applying a program inhibition voltage to an unselected bit line in a first program loop of a plurality of program loops; applying a program permission voltage to a selected bit line in the first program loop; applying a pass voltage to an unselected word line in the first program loop; applying a program voltage to a selected word line in the first program loop; applying a pulse voltage having a polarity opposite to a polarity of the program voltage to the selected word line after applying the program voltage to the selected word line, in the first program loop; and applying a verification voltage to the selected word line after applying the pulse voltage to the selected word line, in the first program loop.
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公开(公告)号：US20240397726A1
公开(公告)日：2024-11-28
申请号：US18655488
申请日：2024-05-06
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ilho Myeong , Yongseok Kim , Taeyoung Kim , Suseong Noh , Sanghyun Park , Suhwan Lim , Daewon Ha
Abstract: A semiconductor device includes a stacked structure including a plurality of gate lines and a plurality of insulation patterns that are alternately stacked in a vertical direction, where the stacked structure defines a vertical hole that extends into the stacked structure and in the vertical direction, a channel film that extends into a vertical hole, and a multiple dielectric layer structure between the channel film and the stacked structure, where the multiple dielectric layer structure includes a plurality of interlayer dielectric layers and a plurality of ferroelectric layers that are alternately stacked and extend from the channel film toward the stacked structure, and where an inner ferroelectric layer of the plurality of ferroelectric layers is thicker than an outer ferroelectric layer of the plurality of ferroelectric layers.
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公开(公告)号：US20240015975A1
公开(公告)日：2024-01-11
申请号：US18108722
申请日：2023-02-13
Applicant: Samsung Electronics Co., Ltd.
Inventor： Suseong Noh , Yongseok Kim , Daewon Ha
Abstract: A semiconductor device may include first conductive lines on a substrate and spaced apart from each other in a first direction, second conductive lines spaced apart from the first conductive lines in a second direction, third conductive lines spaced apart from the second conductive lines in the second direction, gate electrodes between the first, second and third conductive lines and extending in the first direction, ferroelectric patterns on respective side surfaces of the gate electrodes, gate insulating patterns on the respective side surfaces of the gate electrodes and spaced apart from the respective side surfaces of the gate electrodes with the ferroelectric patterns respectively therebetween, and channel patterns extending along respective side surfaces of the gate insulating patterns. Each of the channel patterns may be electrically connected to the second conductive lines, respectively, and may be electrically connected to the first conductive lines or the third conductive lines, respectively.
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