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公开(公告)号：US11988495B2
公开(公告)日：2024-05-21
申请号：US17156049
申请日：2021-01-22
发明人： Kwangsoo Kim , Sungyoon Ryu , Daejun Park , Seong Yun , Seungryeol Oh , Sujin Lee , Jaeyong Lee , Minho Rim , Chungsam Jun , Myungjun Lee
CPC分类号： G01B11/02 , G01N21/8806 , G01N21/8851 , G03F7/70625 , G03F7/7065 , G01B2210/56 , G01N2021/8887
摘要： Provided is a through-focus image-based metrology device including an optical device, and a computing device configured to acquire at least one through-focus image of a target from the optical device, generate an intensity profile based on the acquired at least one through-focus image, and perform metrology on the target based on the generated intensity profile, wherein the optical device includes a stage on which the target is disposed, the stage being configured to move by one step in at least one direction based on control of the computing device, and to acquire the at least one through-focus image, an image sensor disposed on the stage, an objective lens disposed between the image sensor and the stage, the objective lens being configured to transmit reflected light from the target, and a light source configured to emit illumination light to the target through the objective lens.
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2.发明授权公开(公告)号：US10699927B1
公开(公告)日：2020-06-30
申请号：US16509835
申请日：2019-07-12
发明人： Wookrae Kim , Kwangsoo Kim , Gwangsik Park
IPC分类号： G01N21/00 , H01L21/67 , H01L21/66 , H01L27/22 , G01N21/88 , H01L43/12 , G01N21/95 , H01L43/02
摘要： An inspection apparatus includes a first optical module including a first light source configured to emit first light to a semiconductor structure, a second light source configured to emit second light different from the first light to a portion adjacent to a portion to which the first light is emitted in the semiconductor structure, a detector configured to detect the second light reflected toward the second light source, and a lock-in amplifier connected to the first optical module and the detector.
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公开(公告)号：US20210396510A1
公开(公告)日：2021-12-23
申请号：US17156049
申请日：2021-01-22
发明人： Kwangsoo Kim , Sungyoon Ryu , Daejun Park , Seong Yun , Seungryeol Oh , Sujin Lee , Jaeyong Lee , Minho Rim , Chungsam Jun , Myungjun Lee
摘要： Provided is a through-focus image-based metrology device including an optical device, and a computing device configured to acquire at least one through-focus image of a target from the optical device, generate an intensity profile based on the acquired at least one through-focus image, and perform metrology on the target based on the generated intensity profile, wherein the optical device includes a stage on which the target is disposed, the stage being configured to move by one step in at least one direction based on control of the computing device, and to acquire the at least one through-focus image, an image sensor disposed on the stage, an objective lens disposed between the image sensor and the stage, the objective lens being configured to transmit reflected light from the target, and a light source configured to emit illumination light to the target through the objective lens.
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公开(公告)号：US11158651B2
公开(公告)日：2021-10-26
申请号：US16773103
申请日：2020-01-27
发明人： Kyunghwan Lee , Kwangsoo Kim , Taehun Kim , Yongseok Kim , Kohji Kanamori
IPC分类号： H01L29/792 , H01L27/11582 , G11C16/04 , G11C5/02
摘要： A vertical memory device includes gate electrodes on a substrate. The gate electrodes are spaced apart from each other in a vertical direction. A channel penetrates the gate electrodes and extends in the vertical direction. A tunnel insulation pattern is formed on an outer sidewall of the channel. A charge trapping pattern structure is formed on an outer sidewall of the tunnel insulation pattern adjacent the gate electrodes in a horizontal direction. The charge trapping pattern structure includes upper and lower charge trapping patterns. A blocking pattern is formed between the charge trapping pattern structure and each of the adjacent gate electrodes. An upper surface of the upper charge trapping pattern is higher than an upper surface of the adjacent gate electrode. A lower surface of the lower charge trapping pattern is lower than a lower surface of an adjacent gate electrode.
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公开(公告)号：US11387184B2
公开(公告)日：2022-07-12
申请号：US16885933
申请日：2020-05-28
发明人： Junhyoung Kim , Joongshik Shin , Kwangsoo Kim
IPC分类号： H01L23/535 , H01L27/11524 , H01L27/11556 , H01L27/11529 , H01L27/1157 , H01L27/11582 , H01L21/768 , H01L23/522 , H01L23/528 , H01L27/11573
摘要： A three-dimensional semiconductor device may include a substrate having a cell area and an extension area, a word line stack disposed above the substrate, the word line stack including mold layers and word lines alternately stacked, vertical channel structures vertically penetrating the word line stack in the cell area, and a first extension through-via structure vertically penetrating the word line stack in the extension area. The first extension through-via structure may include a first via plug and a first via liner layer surrounding sidewalls of the first via plug. The first via liner layer may include first dents respectively disposed at the same levels horizontally as the word lines of the word line stack.
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