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公开(公告)号：US12029029B2
公开(公告)日：2024-07-02
申请号：US17716215
申请日：2022-04-08
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kyunghwan Lee , Yongseok Kim , Hyuncheol Kim , Dongsoo Woo , Sungwon Yoo
IPC: H10B12/00 , H01L29/423 , H01L29/792
CPC classification number: H10B12/50 , H01L29/4234 , H01L29/7926
Abstract: A semiconductor memory device includes a semiconductor substrate a gate structure extending in a vertical direction on the semiconductor device, a plurality of charge trap layers spaced apart from each other in the vertical direction and each having a horizontal cross-section with a first ring shape surrounding the gate structure, a plurality of semiconductor patterns spaced apart from each other in the vertical direction and each having a horizontal cross-section with a second ring shape surrounding the plurality of charge trap layers, a source region and a source line at one end of each of the plurality of semiconductor patterns in a horizontal direction, and a drain region and a drain line at an other end of each of the plurality of semiconductor patterns in the horizontal direction. The gate structure may include a gate insulation layer and a gate electrode layer.
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公开(公告)号：US12016188B2
公开(公告)日：2024-06-18
申请号：US17840213
申请日：2022-06-14
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyuncheol Kim , Yongseok Kim , Dongsoo Woo , Kyunghwan Lee
CPC classification number: H10K19/202 , G11C13/0014 , G11C13/0069 , H10K10/50 , H10K85/221
Abstract: A semiconductor memory device includes a plurality of semiconductor patterns extending in a first horizontal direction and separated from each other in a second horizontal direction and a vertical direction, each semiconductor pattern including a first source/drain area, a channel area, and a second source/drain area arranged in the first horizontal direction; a plurality of gate insulating layers covering upper surfaces or side surfaces of the channel areas; a plurality of word lines on the upper surfaces or the side surfaces of the channel areas; and a plurality of resistive switch units respectively connected to first sidewalls of the semiconductor patterns, extending in the first horizontal direction, and separated from each other in the second horizontal direction and the vertical direction, each resistive switch unit including a first electrode, a second electrode, and a resistive switch material layer between the first and second electrodes and including carbon nanotubes.
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公开(公告)号：US11670679B2
公开(公告)日：2023-06-06
申请号：US17225716
申请日：2021-04-08
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kyunghwan Lee , Yongseok Kim , Hyuncheol Kim , Sungwon Yoo , Jaeho Hong
IPC: H01L29/00 , H01L29/10 , H01L29/786 , H01L29/06
CPC classification number: H01L29/1033 , H01L29/0615 , H01L29/7869 , H01L29/78642
Abstract: A semiconductor device includes a gate electrode on a substrate, a channel surrounding sidewalls of the gate electrode on the substrate, and source/drain electrodes on the substrate at opposite sides of the gate electrode in a first direction parallel to an upper surface of the substrate. A thickness of the channel from the gate electrode to the source/drain electrodes in a horizontal direction parallel to the upper surface of the substrate is not constant but varies in a vertical direction perpendicular to the upper surface of the substrate.
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公开(公告)号：US20230112070A1
公开(公告)日：2023-04-13
申请号：US17836228
申请日：2022-06-09
Applicant: Samsung Electronics Co., Ltd.
Inventor： Minjun Lee , Yongseok Kim , Hyuncheol Kim , Jongman Park , Dongsoo Woo , Kyunghwan Lee
Abstract: Provided is a memory device. The memory device may include a substrate, a ferroelectric field effect transistor disposed on the substrate, a first channel contacting a gate structure of the ferroelectric field effect transistor and extending in a vertical direction from the gate structure of the ferroelectric field effect transistor, a selection word line disposed at one side of the first channel, a first gate dielectric layer disposed between the first channel and the selection word line, and a cell word line disposed on top of the first channel.
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公开(公告)号：US11606704B2
公开(公告)日：2023-03-14
申请号：US17168918
申请日：2021-02-05
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyunseok Ryu , Yongseok Kim , Peng Xue , Hyunkyu Yu , Sangwon Choi , Kuyeon Whang
Abstract: A communication method and system for converging a 5th-Generation (5G) communication system for supporting higher data rates beyond a 4th-Generation (4G) system with a technology for Internet of Things (IoT) are provided, which may be applied to intelligent services based on the 5G communication technology and the IoT-related technology, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. An uplink transmission method is provided, which can increase an uplink coverage through improvement of reception reliability of uplink control information and data information.
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Patent Agency Ranking
公开(公告)号：US11147029B2
公开(公告)日：2021-10-12
申请号：US16621024
申请日：2018-06-11
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yongseok Kim , Hyunseok Ryu , Hyunkyu Yu
Abstract: The present disclosure relates to a communication technique for convergence of a 5G communication system for supporting a higher data transmission rate beyond a 4G system with an IoT technology, and a system therefor. The present disclosure may be applied to an intelligent service (for example, smart home, smart building, smart city, smart car or connected car, health care, digital education, retail business, security and safety-related service, etc.) on the basis of a 5G communication technology and an IoT-related technology. The present invention relates to a method for controlling power of a terminal in a beamforming system and, specifically, provides a method for supporting control of uplink power of a terminal according to a beam change.
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公开(公告)号：US10979123B2
公开(公告)日：2021-04-13
申请号：US15806132
申请日：2017-11-07
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seokki Ahn , Kwangtaik Kim , Yongseok Kim , Chiwoo Lim
IPC: H04B7/06 , H04L1/00 , H04B7/0452 , H04B7/0408 , H04L5/00
Abstract: The present disclosure relates to a communication method and system for converging a 5th-Generation (5G) communication system for supporting higher data rates beyond a 4th-Generation (4G) system with a technology for Internet of Things (IoT). The present disclosure may be applied to intelligent services based on the 5G communication technology and the IoT-related technology, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services.
According to various embodiments of the present disclosure, a CQI transmission method of a terminal in a wireless communication system includes: estimating a channel of a serving base station and an interference base station to which sliding-window superposition coding (SWSC) is applied; generating channel quality information (CQI)-related information on the serving base station and the interference base station based on the estimated channel to indicate an achievable rate region; and transmitting the generated CQI-related information. However, the present disclosure is not limited to the above embodiment, and therefore other embodiments are possible.-
公开(公告)号：US10978480B2
公开(公告)日：2021-04-13
申请号：US16856663
申请日：2020-04-23
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kyunghwan Lee , Yongseok Kim , Byoung-Taek Kim , Tae Hun Kim , Dongkyun Seo , Junhee Lim
IPC: H01L27/11582 , H01L27/11565 , H01L29/51 , H01L29/423 , H01L27/1157 , H01L27/11556 , H01L27/11524
Abstract: A three-dimensional semiconductor memory device includes an electrode structure including gate electrodes and insulating layers, which are alternately stacked on a substrate, a semiconductor pattern extending in a first direction substantially perpendicular to a top surface of the substrate and penetrating the electrode structure, a tunnel insulating layer disposed between the semiconductor pattern and the electrode structure, a blocking insulating layer disposed between the tunnel insulating layer and the electrode structure, and a charge storing layer disposed between the blocking insulating layer and the tunnel insulating layer. The charge storing layer includes a plurality of first charge trap layers having a first energy band gap, and a second charge trap layer having a second energy band gap larger than the first energy band gap. The first charge trap layers are embedded in the second charge trap layer between the gate electrodes and the semiconductor pattern.
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公开(公告)号：US10694409B2
公开(公告)日：2020-06-23
申请号：US16054504
申请日：2018-08-03
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyunseok Ryu , Yongseok Kim , Peng Xue , Hyunkyu Yu , Sangwon Choi , Kuyeon Whang
Abstract: The fifth generation (5G) or pre-5G communication system for supporting a higher data rate after a fourth generation (4G) communication system like a long term evolution (LTE) are provided. An uplink transmission method is provided, which can increase an uplink coverage through improvement of reception reliability of uplink control information and data information.
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公开(公告)号：US12249651B2
公开(公告)日：2025-03-11
申请号：US17741219
申请日：2022-05-10
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyuncheol Kim , Yongseok Kim , Dongsoo Woo , Kyunghwan Lee
IPC: H01L29/78 , H01L29/10 , H01L29/417
Abstract: A semiconductor device includes: a channel; a gate structure on the channel; a first source/drain arranged at a first end of the channel and including a metal; a first tunable band-gap layer arranged between the channel and the first source/drain and having a band gap that changes according to stress; a first electrostrictive layer between the gate structure and the first tunable band-gap layer, the first electrostrictive layer having a property of being deformed based on and upon application of an electric field; and a second source/drain at a second end of the channel.
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