公开(公告)号：US20250133742A1

公开(公告)日：2025-04-24

申请号：US18783638

申请日：2024-07-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Suseong Noh ,  Ilho Myeong ,  Kwang-Soo Kim

IPC: H10B51/20 ,  H10B51/30

Abstract: A semiconductor device includes: a substrate, a gate stacking structure that includes a plurality of interlayer insulating layers and a plurality of gate electrodes that are alternately stacked on the substrate, a channel layer that extends in a first direction and into the gate stacking structure, where the channel layer is electrically connected to the substrate, a channel insulating layer that at least partially surrounds the channel layer, and a plurality of dielectric layers that are between the channel insulating layer and the plurality of gate electrodes, extend along a circumference of the channel layer, and are spaced apart from each other in the first direction, where each of the plurality of dielectric layers includes: a ferroelectric pattern that at least partially surrounds the channel insulating layer, and an anti-ferroelectric pattern that at least partially surrounds the ferroelectric pattern.

公开(公告)号：US20250048643A1

公开(公告)日：2025-02-06

申请号：US18588712

申请日：2024-02-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Suseong Noh ,  Sangwoo Han ,  Kwang-Soo Kim ,  Ilho Myeong

IPC: H10B51/20 ,  H10B51/30 ,  H10B51/40

Abstract: The present disclosure relates to a semiconductor device and a data storage system including the device. The semiconductor device has a substrate including a cell array region and a contact region. In the cell array region the semiconductor device has a first horizontal conductive layer, a gate stacking structure including a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked on the substrate. A channel structure extends in a direction crossing into the substrate by penetrating the gate stacking structure in the cell array region, and includes a channel layer connected to the substrate. Surrounding the channel layer is a ferroelectric layer. The first horizontal conductive layer is not in direct contact with the channel layer due to a dummy pattern positioned on the first horizontal conductive layer and disposed between the substrate and the ferroelectric layer.

公开(公告)号：US20240397727A1

公开(公告)日：2024-11-28

申请号：US18658265

申请日：2024-05-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ilho Myeong ,  Yongseok Kim ,  Sangwoo Han

IPC: H10B51/20 ,  H01L25/065 ,  H01L29/78 ,  H10B51/10 ,  H10B80/00

Abstract: A semiconductor device includes: a gate line; a hole extending through the gate line; a channel layer extending lengthwise in a first direction in the hole; a ferroelectric layer arranged between the channel layer and the gate line and extending lengthwise in the first direction in the hole; and a multi-tunneling dielectric structure arranged between the ferroelectric layer and the gate line and extending lengthwise in the first direction in the hole, wherein the multi-tunneling dielectric structure includes: a first silicon oxide film contacting the gate line; a second silicon oxide film spaced apart from the first silicon oxide film in a second direction and contacting the ferroelectric layer, wherein the second direction crosses the first direction; and a silicon oxynitride film disposed between the first silicon oxide film and the second silicon oxide film.

公开(公告)号：US20240064996A1

公开(公告)日：2024-02-22

申请号：US18170136

申请日：2023-02-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiheun Lee ,  Yongseok Kim ,  Hyuncheol Kim ,  Ilho Myeong ,  Daewon Ha

IPC: H10B51/20 ,  H10B51/10 ,  H01L23/528 ,  H01L29/51 ,  H01L29/78

CPC classification number: H10B51/20 ,  H10B51/10 ,  H01L23/5283 ,  H01L29/516 ,  H01L29/78391

Abstract: A semiconductor device includes first and second cell arrays. The first cell array includes a first gate electrode that extends in a vertical direction, a first channel pattern on a side surface of the first gate electrode, and a first bit line electrically connected to the first channel pattern. The second cell array includes a second gate electrode that extends in the vertical direction, a second channel pattern on a side surface of the second gate electrode, and a second bit line electrically connected to the second channel pattern. A first bit line pad is electrically connected to the first bit line and a second bit line pad is electrically connected to the second bit line. The first bit line pad is spaced apart from the second bit line pad with the first and second cell arrays therebetween.

公开(公告)号：US20250142834A1

公开(公告)日：2025-05-01

申请号：US18732268

申请日：2024-06-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Suseong Noh ,  Ilho Myeong ,  KWANG-SOO KIM

IPC: H10B51/30 ,  H10B51/20

Abstract: A semiconductor device includes: a substrate; a gate stacking structure that includes interlayer insulating layers and gate electrodes that are alternately stacked on the substrate; a channel structure that penetrates the gate stacking structure and extends in a first direction, and includes a channel layer connected to the substrate and a ferroelectric layer that surrounds the channel layer; a charge inflow pattern disposed on a lateral side of the ferroelectric layer and spaced apart in the first direction; and an insulation pattern disposed between the charge inflow pattern and the gate electrodes and that surrounds an exterior side, a lower side, and an upper side of the charge inflow pattern.

公开(公告)号：US20250095759A1

公开(公告)日：2025-03-20

申请号：US18796585

申请日：2024-08-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ilho Myeong ,  Kwangsoo Kim ,  Suseong Noh

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/32

Abstract: A method of operating a memory device, the method including: applying a program inhibition voltage to an unselected bit line in a first program loop of a plurality of program loops; applying a program permission voltage to a selected bit line in the first program loop; applying a pass voltage to an unselected word line in the first program loop; applying a program voltage to a selected word line in the first program loop; applying a pulse voltage having a polarity opposite to a polarity of the program voltage to the selected word line after applying the program voltage to the selected word line, in the first program loop; and applying a verification voltage to the selected word line after applying the pulse voltage to the selected word line, in the first program loop.

公开(公告)号：US20240397726A1

公开(公告)日：2024-11-28

申请号：US18655488

申请日：2024-05-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ilho Myeong ,  Yongseok Kim ,  Taeyoung Kim ,  Suseong Noh ,  Sanghyun Park ,  Suhwan Lim ,  Daewon Ha

IPC: H10B51/20 ,  H01L25/065 ,  H01L29/66 ,  H01L29/78 ,  H10B51/10 ,  H10B80/00

Abstract: A semiconductor device includes a stacked structure including a plurality of gate lines and a plurality of insulation patterns that are alternately stacked in a vertical direction, where the stacked structure defines a vertical hole that extends into the stacked structure and in the vertical direction, a channel film that extends into a vertical hole, and a multiple dielectric layer structure between the channel film and the stacked structure, where the multiple dielectric layer structure includes a plurality of interlayer dielectric layers and a plurality of ferroelectric layers that are alternately stacked and extend from the channel film toward the stacked structure, and where an inner ferroelectric layer of the plurality of ferroelectric layers is thicker than an outer ferroelectric layer of the plurality of ferroelectric layers.