公开(公告)号：US11903197B2

公开(公告)日：2024-02-13

申请号：US17148334

申请日：2021-01-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Suhwan Lim ,  Jaehun Jung ,  Sanghoon Kim ,  Taehun Kim ,  Seongchan Lee

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/40

CPC classification number: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/40

Abstract: A semiconductor device includes gate electrodes and insulating layers spaced apart from each other on a substrate and alternately stacked in a direction perpendicular to an upper surface of the substrate, and channel structures that extend through stack structures. Ones of the structures include a channel insulating layer, a pad layer on the channel insulating layer, and a channel layer. The channel layer includes a first channel region, and a second channel region including a semiconductor material having a length shorter than a length of the first channel region and having an impurity concentration of a first conductivity type and the pad layer includes a semiconductor material doped with a second conductivity type impurity. A height level of a lower surface of the second channel region is lower than a height level of a lower surface of a first erase gate electrode.

公开(公告)号：US12035521B2

公开(公告)日：2024-07-09

申请号：US17205563

申请日：2021-03-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaehun Jung ,  Suhwan Lim ,  Hyeyoung Kwon

IPC: H01L27/11556 ,  G11C5/06 ,  H01L23/538 ,  H01L27/11582 ,  H10B41/27 ,  H10B43/27

CPC classification number: H10B41/27 ,  G11C5/06 ,  H01L23/5386 ,  H10B43/27

Abstract: A semiconductor device includes a substrate, a stack structure including interlayer insulating layers and gate electrodes alternately and repeatedly stacked on the substrate in a first direction perpendicular, a channel structure that penetrates the stack structure, a contact plug disposed on the channel structure, and a bit line on the contact plug. The channel structure includes a core pattern, a pad structure on the core pattern, and a channel layer on a side surface of the core pattern and a side surface of the pad structure. The pad structure includes a pad pattern, a first pad layer, and a second pad layer, the first pad layer that is between the channel layer and the pad pattern, and the second pad layer including a first portion between the channel layer and the first pad layer, and a second portion between the first pad layer and the core pattern.

公开(公告)号：US12213316B2

公开(公告)日：2025-01-28

申请号：US17720376

申请日：2022-04-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Suhwan Lim ,  Nambin Kim ,  Samki Kim ,  Taehun Kim ,  Hanvit Yang ,  Changhee Lee ,  Jaehun Jung ,  Hyeongwon Choi

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/35 ,  H10B43/40

Abstract: A semiconductor device includes a lower structure including a semiconductor substrate and circuit devices on the semiconductor substrate; a stack structure including interlayer insulating layers and gate electrodes alternating in a vertical direction; and a channel structure penetrating the stack structure. The channel structure includes a core insulating layer, a channel layer, a gate dielectric layer, and a channel pad. A portion of the channel pad overlaps an uppermost gate electrode among the gate electrodes in a horizontal direction. The channel pad includes a first pad layer and a second pad layer on the first pad layer. The second pad layer includes doped polysilicon that is doped with impurities and having N-type conductivity. The first pad layer includes at least one of an undoped polysilicon region and a doped polysilicon region having N-type conductivity and having an impurity concentration lower than an impurity concentration of the second pad layer.

公开(公告)号：US12075615B2

公开(公告)日：2024-08-27

申请号：US17205563

申请日：2021-03-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaehun Jung ,  Suhwan Lim ,  Hyeyoung Kwon

IPC: H01L27/11556 ,  G11C5/06 ,  H01L23/538 ,  H01L27/11582 ,  H10B41/27 ,  H10B43/27

CPC classification number: H10B41/27 ,  G11C5/06 ,  H01L23/5386 ,  H10B43/27

Abstract: A semiconductor device includes a substrate, a stack structure including interlayer insulating layers and gate electrodes alternately and repeatedly stacked on the substrate in a first direction perpendicular, a channel structure that penetrates the stack structure, a contact plug disposed on the channel structure, and a bit line on the contact plug. The channel structure includes a core pattern, a pad structure on the core pattern, and a channel layer on a side surface of the core pattern and a side surface of the pad structure. The pad structure includes a pad pattern, a first pad layer, and a second pad layer, the first pad layer that is between the channel layer and the pad pattern, and the second pad layer including a first portion between the channel layer and the first pad layer, and a second portion between the first pad layer and the core pattern.

公开(公告)号：US20240397726A1

公开(公告)日：2024-11-28

申请号：US18655488

申请日：2024-05-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ilho Myeong ,  Yongseok Kim ,  Taeyoung Kim ,  Suseong Noh ,  Sanghyun Park ,  Suhwan Lim ,  Daewon Ha

IPC: H10B51/20 ,  H01L25/065 ,  H01L29/66 ,  H01L29/78 ,  H10B51/10 ,  H10B80/00

Abstract: A semiconductor device includes a stacked structure including a plurality of gate lines and a plurality of insulation patterns that are alternately stacked in a vertical direction, where the stacked structure defines a vertical hole that extends into the stacked structure and in the vertical direction, a channel film that extends into a vertical hole, and a multiple dielectric layer structure between the channel film and the stacked structure, where the multiple dielectric layer structure includes a plurality of interlayer dielectric layers and a plurality of ferroelectric layers that are alternately stacked and extend from the channel film toward the stacked structure, and where an inner ferroelectric layer of the plurality of ferroelectric layers is thicker than an outer ferroelectric layer of the plurality of ferroelectric layers.