公开(公告)号：US20220216150A1

公开(公告)日：2022-07-07

申请号：US17409069

申请日：2021-08-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongchan Shin ,  Woojeong Shin ,  Changmin Park ,  Noyoung Chung

IPC: H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/417 ,  H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/768

Abstract: A semiconductor device includes a logic cell on a substrate and a first metal layer on the logic cell. The first metal layer includes first and second power lines that extend in a first direction, and first, second, and third lower interconnection lines, which are respectively disposed on first, second, and third interconnection tracks defined between the first and second power lines that extend in the first direction parallel to each other. The first lower interconnection line includes first and second interconnection lines spaced apart from each other by a first distance, and the third lower interconnection line includes third and fourth interconnection lines spaced apart from each other by a second distance. The first and third interconnection lines have first and second ends, respectively, which face the second and fourth interconnection lines, respectively, and have different curvatures.

公开(公告)号：US11830737B2

公开(公告)日：2023-11-28

申请号：US17520634

申请日：2021-11-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hanhum Park ,  Insung Kim ,  Woojeong Shin ,  Jung-Hoon Lee ,  Sanghyeon Kim ,  Ji Young Choi

IPC: H01L21/033

CPC classification number: H01L21/0338 ,  H01L21/0335 ,  H01L21/0337

Abstract: Disclosed are semiconductor device fabricating method and semiconductor device fabricated by the same. The method includes forming on a lower mask layer first upper mask patterns and sacrificial spacers that cover sidewalls of the first upper mask patterns, forming first holes in the lower mask layer below the first upper mask patterns, forming second holes in the lower mask layer not covered by the first upper mask patterns and the sacrificial spacers, forming second upper mask patterns filling a space between the sacrificial spacers on the lower mask layer and also forming sacrificial patterns filling the first and second holes, removing the sacrificial spacers, using the first and second upper mask patterns to etch the lower mask layer, and removing the sacrificial patterns.

公开(公告)号：US11097211B2

公开(公告)日：2021-08-24

申请号：US16567052

申请日：2019-09-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taehoi Park ,  Sangjin Kim ,  Nakhee Seong ,  Woojeong Shin ,  Taehwan Oh ,  Kwangsub Yoon

IPC: B01D35/26 ,  B01D36/00 ,  G03F7/16

Abstract: A resist coating apparatus including a resist supplying system; a resist filtering system having a first filter, a second filter, and a pump between the first filter and the second filter; and a resist dispensing system, wherein the first filter includes a plurality of first unit filters connected in parallel.