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    Semiconductor devices having shielding pattern
    1.
    发明授权
    Semiconductor devices having shielding pattern 有权
    具有屏蔽图案的半导体器件

    公开(公告)号：US09461003B1

    公开(公告)日：2016-10-04

    申请号：US14995467

    申请日：2016-01-14

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Jimyung Kim ,  Yigwon Kim ,  Suhyun Kim ,  Kwangsub Yoon ,  Bumjoon Youn ,  Narak Choi

    IPC分类号： H01L27/146 ,  H01L23/552 ,  H01L23/58 ,  H01L23/544

    CPC分类号： H01L23/552 ,  G03F7/70633 ,  H01L23/5225 ,  H01L23/585

    摘要： A semiconductor device includes a circuit pattern on a substrate, a shielding pattern on the circuit pattern and constituted by a plurality of parallel bars, and lower overlay marking on the shielding pattern and constituted by a plurality of parallel bars which define parallel slits between the bars. The pitch of the bars of the shielding pattern is smaller than the pitch of the bars of the lower overlay marking.

    摘要翻译： 半导体器件包括衬底上的电路图案，电路图案上的屏蔽图案并由多个平行条构成，并且在屏蔽图案上形成下覆盖标记，并且由多个平行的条构成，所述平行条在条之间形成平行的狭缝 。 屏蔽图案的条的间距小于下覆盖标记的条的间距。

    Semiconductor device
    2.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US10096546B2

    公开(公告)日：2018-10-09

    申请号：US15704049

    申请日：2017-09-14

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Changseop Yoon ,  Kwangsub Yoon ,  Jongmil Youn ,  Hyung Jong Lee

    IPC分类号： H01L23/528 ,  H01L21/8238 ,  H01L29/06 ,  H01L27/02 ,  H01L23/485

    摘要： A semiconductor device includes a substrate including PMOSFET and NMOSFET regions, a first gate structure extending in a first direction and crossing the PMOSFET and NMOSFET regions, and a gate contact on and connected to the first gate structure, the gate contact being between the PMOSFET and NMOSFET regions, the gate contact including a first sub contact in contact with a top surface of the first gate structure, the first sub contact including a vertical extending portion extending vertically toward the substrate along one sidewall of the first gate structure, and a second sub contact spaced apart from the first gate structure, a top surface of the second sub contact being positioned at a same level as a top surface of the first sub contact.

    Method of fabricating semiconductor device
    6.
    发明授权
    Method of fabricating semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US09443732B1

    公开(公告)日：2016-09-13

    申请号：US14452243

    申请日：2014-08-05

    申请人： Samsung Electronics Co., Ltd.

    发明人： Tae Sun Kim ,  Jaekyung Seo ,  Kwangsub Yoon ,  Yura Kim ,  Yeojin Lee

    IPC分类号： G03F7/40 ,  H01L21/426 ,  H01L21/266 ,  H01L29/66 ,  H01L21/02

    CPC分类号： H01L29/66795 ,  H01L21/26586 ,  H01L21/823821 ,  H01L29/66803

    摘要： The method may include forming a plurality of fins on a substrate with first and second regions, forming a photoresist pattern to expose the fins of the first region, forming a material layer to cover the fins of first region and the photoresist pattern, chemically reacting the photoresist pattern the material layer to form a supplemental film on a side surface of the photoresist pattern, performing an ion implantation process using the photoresist pattern and the supplemental film as a ion injection mask to form impurity layers in the fins of the first region.

    摘要翻译： 该方法可以包括在第一和第二区域的基板上形成多个翅片，形成光致抗蚀剂图案以暴露第一区域的散热片，形成覆盖第一区域和光致抗蚀剂图案的散热片的材料层，使 光致抗蚀剂图案化材料层以在光致抗蚀剂图案的侧表面上形成补充膜，使用光致抗蚀剂图案和补充膜作为离子注入掩模进行离子注入工艺，以在第一区域的散热片中形成杂质层。

    Semiconductor device
    8.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US10211156B2

    公开(公告)日：2019-02-19

    申请号：US16119475

    申请日：2018-08-31

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Changseop Yoon ,  Kwangsub Yoon ,  Jongmil Youn ,  Hyung Jong Lee

    IPC分类号： H01L23/528 ,  H01L21/8238 ,  H01L27/02 ,  H01L23/485 ,  H01L29/06

    摘要： A semiconductor device includes a substrate including PMOSFET and NMOSFET regions, a first gate structure extending in a first direction and crossing the PMOSFET and NMOSFET regions, and a gate contact on and connected to the first gate structure, the gate contact being between the PMOSFET and NMOSFET regions, the gate contact including a first sub contact in contact with a top surface of the first gate structure, the first sub contact including a vertical extending portion extending vertically toward the substrate along one sidewall of the first gate structure, and a second sub contact spaced apart from the first gate structure, a top surface of the second sub contact being positioned at a same level as a top surface of the first sub contact.