公开(公告)号：US20210167063A1

公开(公告)日：2021-06-03

申请号：US17170252

申请日：2021-02-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moon Gi Cho ,  Hyeonuk Kim ,  Jongchan Shin ,  Eryung Hwang ,  Jaeseok Yang ,  Jinwoo Jeong

IPC: H01L27/088 ,  H01L23/528 ,  H01L29/06 ,  H01L27/02 ,  H01L27/118 ,  H01L29/78

Abstract: Semiconductor devices are provided. A semiconductor device includes a gate structure and an adjacent contact. The semiconductor device includes a connector that is connected to the contact. In some embodiments, the semiconductor device includes a wiring pattern that is connected to the connector. Moreover, in some embodiments, the connector is adjacent a boundary between first and second cells of the semiconductor device.

公开(公告)号：US10930648B2

公开(公告)日：2021-02-23

申请号：US16422199

申请日：2019-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moon Gi Cho ,  Hyeonuk Kim ,  Jongchan Shin ,  Eryung Hwang ,  Jaeseok Yang ,  Jinwoo Jeong

IPC: H01L27/08 ,  H01L27/02 ,  H01L27/11 ,  H01L23/52 ,  H01L29/06 ,  H01L29/78 ,  H01L27/088 ,  H01L23/528 ,  H01L27/118 ,  H01L27/11565 ,  H01L27/11587 ,  H01L27/11519 ,  H01L27/11504 ,  H01L21/8234 ,  H01L23/522 ,  H01L23/532 ,  H01L27/092 ,  H01L29/417

Abstract: Semiconductor devices are provided. A semiconductor device includes a gate structure and an adjacent contact. The semiconductor device includes a connector that is connected to the contact. In some embodiments, the semiconductor device includes a wiring pattern that is connected to the connector. Moreover, in some embodiments, the connector is adjacent a boundary between first and second cells of the semiconductor device.

公开(公告)号：US20180366463A1

公开(公告)日：2018-12-20

申请号：US15926572

申请日：2018-03-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moon Gi Cho ,  Hyeonuk Kim ,  Jongchan Shin ,  Eryung Hwang ,  Jaeseok Yang ,  Jinwoo Jeong

IPC: H01L27/088 ,  H01L29/06 ,  H01L23/528

CPC classification number: H01L27/088 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53233 ,  H01L23/53295 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/11504 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11587 ,  H01L27/11807 ,  H01L29/0646 ,  H01L29/785 ,  H01L2027/11829 ,  H01L2027/11875

Abstract: Semiconductor devices are provided. A semiconductor device includes a gate structure and an adjacent contact. The semiconductor device includes a connector that is connected to the contact. In some embodiments, the semiconductor device includes a wiring pattern that is connected to the connector. Moreover, in some embodiments, the connector is adjacent a boundary between first and second cells of the semiconductor device.

公开(公告)号：US20190287965A1

公开(公告)日：2019-09-19

申请号：US16422199

申请日：2019-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moon Gi Cho ,  Hyeonuk Kim ,  Jongchan Shin ,  Eryung Hwang ,  Jaeseok Yang ,  Jinwoo Jeong

IPC: H01L27/088 ,  H01L29/06 ,  H01L27/02 ,  H01L29/78 ,  H01L27/118 ,  H01L23/528

Abstract: Semiconductor devices are provided. A semiconductor device includes a gate structure and an adjacent contact. The semiconductor device includes a connector that is connected to the contact. In some embodiments, the semiconductor device includes a wiring pattern that is connected to the connector. Moreover, in some embodiments, the connector is adjacent a boundary between first and second cells of the semiconductor device.

公开(公告)号：US10347627B2

公开(公告)日：2019-07-09

申请号：US15926572

申请日：2018-03-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moon Gi Cho ,  Hyeonuk Kim ,  Jongchan Shin ,  Eryung Hwang ,  Jaeseok Yang ,  Jinwoo Jeong

IPC: H01L27/08 ,  H01L27/11 ,  H01L23/52 ,  H01L29/06 ,  H01L27/088 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/11587 ,  H01L27/11519 ,  H01L27/11504

Abstract: Semiconductor devices are provided. A semiconductor device includes a gate structure and an adjacent contact. The semiconductor device includes a connector that is connected to the contact. In some embodiments, the semiconductor device includes a wiring pattern that is connected to the connector. Moreover, in some embodiments, the connector is adjacent a boundary between first and second cells of the semiconductor device.

公开(公告)号：US11658073B2

公开(公告)日：2023-05-23

申请号：US17405134

申请日：2021-08-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongchan Shin ,  Changmin Park

IPC: H01L21/8234 ,  H01L21/308 ,  H01L27/088

CPC classification number: H01L21/8234 ,  H01L21/3086 ,  H01L27/088

Abstract: A semiconductor device includes; a substrate including a first region and a second region adjacent to the first region in a first direction, a pair of active patterns adjacently disposed on the substrate, wherein the pair of active patterns includes a first active pattern extending in the first direction and a second active pattern extending in parallel with the first active pattern, a first gate electrode on the first region and extending in a second direction that intersect the first direction across the first active pattern and the second active pattern, and a second gate electrode on the second region and extending in the second direction across the first active pattern and the second active pattern. A width of the first active pattern is greater on the first region than on the second region, a width of the second active pattern is greater on the first region than on the second region, and an interval between the first active pattern and the second active pattern is constant from the first region to the second region.

公开(公告)号：US20220216150A1

公开(公告)日：2022-07-07

申请号：US17409069

申请日：2021-08-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongchan Shin ,  Woojeong Shin ,  Changmin Park ,  Noyoung Chung

IPC: H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/417 ,  H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/768

Abstract: A semiconductor device includes a logic cell on a substrate and a first metal layer on the logic cell. The first metal layer includes first and second power lines that extend in a first direction, and first, second, and third lower interconnection lines, which are respectively disposed on first, second, and third interconnection tracks defined between the first and second power lines that extend in the first direction parallel to each other. The first lower interconnection line includes first and second interconnection lines spaced apart from each other by a first distance, and the third lower interconnection line includes third and fourth interconnection lines spaced apart from each other by a second distance. The first and third interconnection lines have first and second ends, respectively, which face the second and fourth interconnection lines, respectively, and have different curvatures.

公开(公告)号：US10468252B2

公开(公告)日：2019-11-05

申请号：US16185137

申请日：2018-11-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongchan Shin

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/3105 ,  H01L23/528

Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The method comprises sequentially forming a target layer and a first mask layer on a substrate, patterning the first mask layer to form a first opening in the first mask layer, forming a spacer covering an inner wall of the first opening, forming on the first mask layer a first photoresist pattern having a second opening vertically overlapping at least a portion of the spacer, forming a third opening in the first mask layer that is adjacent to the first opening by using the spacer as a mask to remove a portion of the first mask layer that is exposed to the second opening, and using the first mask layer and the spacer as a mask to pattern the target layer.