公开(公告)号：US20240071841A1

公开(公告)日：2024-02-29

申请号：US18302401

申请日：2023-04-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sumin PARK ,  Taeseong KIM ,  Jaehyung PARK ,  Kyuha LEE ,  Yeojin LEE ,  Kwangjin MOON ,  Hojin LEE

IPC: H01L21/66 ,  B24B37/013 ,  G06F30/392 ,  H01L23/00

CPC classification number: H01L22/20 ,  B24B37/013 ,  G06F30/392 ,  H01L22/32 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/03845 ,  H01L2224/05571 ,  H01L2224/05647

Abstract: In a manufacturing method of a wafer, the method including: an operation of preparing a wafer including a semiconductor chip region and a test region, measuring a measurement region included in the test region with an atomic force microscope (AFM), the measurement region including a plurality of metal lines having a constant line width and a constant pitch; determining a surface roughness value of the test region based on a result of the measuring of the measurement region; determining a step difference value of the metal lines of the test region based on the surface roughness value; and determining a step difference value of bonding pads in the semiconductor chip region based on the step difference value of the metal lines.

公开(公告)号：US20240047211A1

公开(公告)日：2024-02-08

申请号：US18143296

申请日：2023-05-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeojin LEE ,  Hyunjae KANG ,  Sangjin KIM

IPC: H01L21/033 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/027

CPC classification number: H01L21/0337 ,  H01L29/66545 ,  H01L21/823431 ,  H01L21/0276

Abstract: In some embodiments, a method of manufacturing an integrated circuit device includes forming a feature structure on a substrate, forming a first hardmask configured to cover the feature structure, forming, on the first hardmask, a second hardmask comprising a plurality of first line portions extending lengthwise in a first horizontal direction and being apart from each other in a second horizontal direction perpendicular to the first horizontal direction, forming, on at least one of the first hardmask and the second hardmask, an etch mask pattern comprising a plurality of second line portions, forming, from the first hardmask, a first hardmask pattern comprising a plurality of third line portions, forming, from the second hardmask, a plurality of second hardmask patterns, and forming a feature pattern comprising a plurality of fourth line portions by etching the feature structure and using the plurality of second hardmask patterns and the first hardmask pattern.