公开(公告)号：US10818347B2

公开(公告)日：2020-10-27

申请号：US16421855

申请日：2019-05-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ihor Vasyltsov ,  Youngnam Hwang ,  Jinmin Kim ,  Yongha Park ,  Hyunsik Park ,  Jaewon Yang

IPC: G11C11/54 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4096 ,  G06N3/04

Abstract: A semiconductor memory device includes a memory cell array including first memory cells and second memory cell, and a peripheral circuit. When a first command, a first address, and first input data are received, the peripheral circuit reads first data from the first memory cells based on the first address in response to the first command, performs a first operation by using the first data and the first input data, and reads second data from the second memory cells by using a result of the first operation.

公开(公告)号：US20200321059A1

公开(公告)日：2020-10-08

申请号：US16825302

申请日：2020-03-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongha Park ,  Chaehoon Kim ,  Sangwan Nam

IPC: G11C16/24 ,  G11C16/04 ,  G11C16/26 ,  G11C16/30

Abstract: A method controls a memory device that includes a page buffer circuit comprising a plurality of page buffers each comprising at least one latch. The method includes generating by an internal voltage circuit at least one internal voltage among internal voltages used for an operation of the page buffer circuit, the internal voltage circuit providing the at least one internal voltage to the page buffer circuit; and providing to the page buffer circuit a control signal for forming an electrical connection between the internal voltage circuit and a first electrical node of a first page buffer unused for buffering in the page buffer circuit during a set operation for a first latch of a second page buffer.

公开(公告)号：US12086599B2

公开(公告)日：2024-09-10

申请号：US17717302

申请日：2022-04-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehyung Ahn ,  Wooseok Chang ,  Yongha Park

IPC: G06F13/14 ,  G06F9/38 ,  G06F9/48 ,  G06F13/12 ,  G06N3/08

CPC classification number: G06F9/3838 ,  G06F9/3877 ,  G06F9/4881 ,  G06F13/12 ,  G06N3/08 ,  G06F2213/0026

Abstract: A method of operating an accelerator includes receiving, from a central processing unit (CPU), commands for the accelerator and a peripheral device of the accelerator, processing the received commands according to a subject of performance of each of the commands, and transmitting a completion message indicating that performance of the commands is completed to the CPU after the performance of the commands is completed.

公开(公告)号：US11232038B2

公开(公告)日：2022-01-25

申请号：US16890169

申请日：2020-06-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ihor Vasyltsov ,  Youngnam Hwang ,  Yongha Park

IPC: G06F12/0875 ,  G11C15/00 ,  G06N20/00

Abstract: A ternary content addressable memory device (TCAM) may include: a cache memory storing a look-up table with respect to a calculation result of a plurality of functions; an approximation unit configured to generate mask bits; and a controller configured to obtain an approximation input value corresponding to an input key based on the mask bits and to retrieve an output value corresponding to the obtained approximation input value from the look-up table.

公开(公告)号：US09766875B2

公开(公告)日：2017-09-19

申请号：US14470172

申请日：2014-08-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yongha Park ,  Hyunsuk Kim ,  Jinaeon Lee

IPC: G06T1/20 ,  G06F9/445

CPC classification number: G06F8/65 ,  G06T1/20 ,  Y02D10/42

Abstract: A method of processing multimedia data includes: separating a defined application kernel into a data patch kernel and a data processing kernel; requesting, by the data processing kernel, access to patch data of the multimedia data, from the data patch kernel; performing, by the data patch kernel, an operation that is independent of the request and preparing data for the data access based on the request; and performing, by the data processing kernel, an arithmetic operation on work items of the prepared data when the data has been prepared by the data patch kernel.

公开(公告)号：US11966736B2

公开(公告)日：2024-04-23

申请号：US16922257

申请日：2020-07-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongha Park

IPC: G06F9/30 ,  G06F9/34 ,  G06F9/38 ,  G06F13/16

CPC classification number: G06F9/3004 ,  G06F9/3001 ,  G06F9/34 ,  G06F9/3877 ,  G06F13/1668

Abstract: An interconnect device may include one or more hardware-implemented modules configured to: receive a command from a processing core; perform, based on the received command, an operation including either one or both of an accumulation of sets of data stored in a memory and an aggregation of results processed by the processing core; and provide a result of the performing of the operation.

公开(公告)号：US10984873B2

公开(公告)日：2021-04-20

申请号：US16825302

申请日：2020-03-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongha Park ,  Chaehoon Kim ,  Sangwan Nam

IPC: G11C16/24 ,  G11C16/04 ,  G11C16/30 ,  G11C16/26 ,  H01L27/11582 ,  H01L27/11556

Abstract: A method controls a memory device that includes a page buffer circuit comprising a plurality of page buffers each comprising at least one latch. The method includes generating by an internal voltage circuit at least one internal voltage among internal voltages used for an operation of the page buffer circuit, the internal voltage circuit providing the at least one internal voltage to the page buffer circuit; and providing to the page buffer circuit a control signal for forming an electrical connection between the internal voltage circuit and a first electrical node of a first page buffer unused for buffering in the page buffer circuit during a set operation for a first latch of a second page buffer.

公开(公告)号：US10043235B2

公开(公告)日：2018-08-07

申请号：US14539609

申请日：2014-11-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Cheolkyoo Kim ,  Kilwhan Lee ,  Yongha Park

IPC: G06T1/60 ,  G06F12/08 ,  G06F12/0862

Abstract: Provided are a multimedia data processing system and a selective caching method. The selective caching method in the multimedia data processing system includes inserting cacheability indicator information into an address translation table descriptor undergoing memory allocation to a graphics resource when the graphics resource needs to be cached and selectively controlling whether or not to prefetch multimedia data of the graphics resource present in a main memory to a system level cache memory, with reference to cacheability indicator information during an address translation operation of a graphic processing unit (GPU). The inventive concept can be implemented in a wide variety of computer-based systems having a graphical output, such as cell phones, laptops, tablets, and personal computers, as only a few examples.

公开(公告)号：US20150234664A1

公开(公告)日：2015-08-20

申请号：US14618124

申请日：2015-02-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyo-Eun Kim ,  Chang-Hyo Yu ,  Seok-Hoon Kim ,  Yongha Park ,  Kilwhan Lee

IPC: G06F9/38 ,  G06F12/08 ,  G06F9/30

CPC classification number: G06F9/3834 ,  G06F9/3824 ,  G06F9/3838 ,  G06F9/3851 ,  G06F12/0868 ,  Y02D10/13

Abstract: A multimedia data processing method is provided which includes providing a conflict detection unit at a load/store pipeline unit; generating, by the conflict detection unit, speculative conflict information, which is used to predictively determine whether an address of a load/store instruction of a current thread causes a conflict miss before a cache access operation is performed by performing a history search for load/store instruction addresses of previous threads without referring to a cache memory; and storing information of the current thread directly in a standby buffer without an execution of the cache access operation in response to the generated speculative conflict information indicating the conflict miss.

Abstract translation: 提供了一种多媒体数据处理方法，其包括在加载/存储流水线单元处提供冲突检测单元; 由冲突检测单元产生用于预测性地确定当前线程的加载/存储指令的地址是否在执行高速缓存访​​问操作之前引起冲突未命中的推测性冲突信息，通过执行用于加载/ 存储先前线程的指令地址而不参考高速缓冲存储器; 以及响应于所产生的表示冲突未决的猜测冲突信息，将当前线程的信息直接存储在备用缓冲器中，而不执行高速缓存访​​问操作。