公开(公告)号：US20240404570A1

公开(公告)日：2024-12-05

申请号：US18581187

申请日：2024-02-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki-Seok PARK ,  Do-Han KIM ,  Minsu BAE ,  Chang-Hyun BAE ,  Young-Hoon SON ,  Hye-Seung YU ,  Yoenhwa LEE ,  Daihyun LIM ,  Insu CHOI ,  Kideok HAN

IPC: G11C7/22 ,  G11C7/10

Abstract: A method of training a memory device is provided. In first to third DCA training steps, a score for each of first to third DCA code combinations is calculated based on an eye window size of a data signal, and in response to a tie occurring among scores, a DCA code combination is selected based on the sum of an even-eye window minimum value and an odd-eye window minimum value of the data signal.

公开(公告)号：US20220138045A1

公开(公告)日：2022-05-05

申请号：US17398158

申请日：2021-08-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jun Young PARK ,  Young-Hoon SON ,  Hyun-Yoon CHO ,  Young Don CHOI ,  Jung Hwan CHOI

IPC: G06F11/10 ,  H03M13/29 ,  G06F1/08

Abstract: A memory device includes a multiphase clock generator which generates a plurality of divided clock signals, a first error correction block which receives a first divided clock signal among the plurality of divided clock signals, a first data multiplexer which transmits first least significant bit data corresponding to the first divided clock signal, a second error correction block which receives the first divided clock signal, and a second data multiplexer which transmits first most significant bit data corresponding to the first divided clock signal. The first error correction block receives the first least significant bit data and corrects a toggle timing of the first least significant bit data. The second error correction block receives the first most significant bit data and corrects a toggle time of the first most significant bit data.

公开(公告)号：US20240321338A1

公开(公告)日：2024-09-26

申请号：US18529283

申请日：2023-12-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kideok HAN ,  Ki-Seok PARK ,  Young-Hoon SON ,  Do-Han KIM ,  Min-Su BAE ,  Yoenhwa LEE ,  Insu CHOI

IPC: G11C11/4076 ,  G11C11/4096

CPC classification number: G11C11/4076 ,  G11C11/4096

Abstract: A training method of a memory device adjusting an eye window of a data signal in response to a duty cycle adjuster (DCA) includes performing a first training operation that selects a first DCA code corresponding to a first internal clock signal having a phase difference of 180° relative to a reference internal clock signal, and performing a second training operation that selects a second DCA code and a third DCA code respectively corresponding to a second internal clock signal and a third internal clock signal having a phase difference of 90° and 270° relative to reference internal clock signal. In the first training operation, the eye window size of the data signal is measured in units of two unit intervals, and in the second training operation, the eye window size of the data signal is measured in units of one unit interval.

公开(公告)号：US20210327476A1

公开(公告)日：2021-10-21

申请号：US17355765

申请日：2021-06-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DONGHUN LEE ,  Daesik MOON ,  Young-Soo SOHN ,  Young-Hoon SON ,  Ki-Seok OH ,  Changkyo LEE ,  Hyun-Yoon CHO ,  Kyung-Soo HA ,  Seokhun HYUN

IPC: G11C7/10 ,  G06F3/06

Abstract: A memory device includes a driver that drives a data line connected with an external device, an internal ZQ manager that generates an internal ZQ start signal, a selector that selects one of the internal ZQ start signal and a ZQ start command from the external device, based on a ZQ mode, a ZQ calibration engine that generates a ZQ code by performing ZQ calibration in response to a selection result of the selector, and a ZQ code register that loads the ZQ code onto the driver in response to a ZQ calibration command from the external device.

公开(公告)号：US20190189592A1

公开(公告)日：2019-06-20

申请号：US16105202

申请日：2018-08-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-Hoon SON ,  Jung-Hwan CHOI ,  Seok-Hun HYUN

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L24/02 ,  H01L2224/02379 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/1434

Abstract: A semiconductor package includes a first layer including a first semiconductor chip and a first through via, a first redistribution layer disposed on a surface of the first layer, and including a first-first wiring and a second-first wiring, and a second layer including a second semiconductor chip, and stacked on the first layer. The first semiconductor chip includes a first-first buffer, and the first-first buffer is electrically connected between the first-first wiring and the second-first wiring.

公开(公告)号：US20190354292A1

公开(公告)日：2019-11-21

申请号：US16524749

申请日：2019-07-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seong-Il O ,  Nam Sung KIM ,  Young-Hoon SON ,  Chan-Kyung KIM ,  Ho-Young SONG ,  Jung Ho AHN ,  Sang-Joon HWANG

IPC: G06F3/06 ,  G06F13/16

Abstract: A memory module includes a memory device, a command/address buffering device, and a processing data buffer. The memory device includes a memory cell array, a first set of input/output terminals, each terminal configured to receive first command/address bits, and a second set of input/output terminals, each terminal configured to receive both data bits and second command/address bits. The command/address buffering device is configured to output the first command/address bits to the first set of input/output terminals. The processing data buffer is configured to output the data bits and second command/address bits to the second set of input/output terminals. The memory device is configured such that the first command/address bits, second command/address bits, and data bits are all used to access the memory cell array.

公开(公告)号：US20190181109A1

公开(公告)日：2019-06-13

申请号：US16036198

申请日：2018-07-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sihong KIM ,  Young-Hoon SON ,  Taeyoung OH ,  Kyung-Soo HA

IPC: H01L23/00 ,  G11C5/06 ,  G11C8/10

Abstract: A semiconductor memory includes a plurality of first pads arranged in a first direction, a plurality of second pads arranged parallel to the plurality of first pads and in the first direction, a plurality of third pads arranged in a second direction perpendicular to the first direction, and a plurality of fourth pads arranged in the second direction. The semiconductor memory further includes first interconnection wires extending from the plurality of first pads in the second direction, the first interconnection wires being connected to the plurality of third pads, and second interconnection wires extending from the plurality of second pads in an opposite direction to the second direction, the second interconnection wires being connected to the plurality of fourth pads.

公开(公告)号：US20140268978A1

公开(公告)日：2014-09-18

申请号：US14144470

申请日：2013-12-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyo-Jin CHOI ,  Su-A KIM ,  Young-Hoon SON ,  Jung-Ho AHN ,  Hak-Soo YU ,  Jae-Youn YOUN

IPC: G11C5/06

CPC classification number: G11C5/063 ,  G11C5/025 ,  G11C11/4093 ,  G11C11/4097 ,  G11C2207/105

Abstract: A semiconductor memory device may include a plurality of data input/output DQ pads and a plurality of first and second memory cell arrays. Each path of a first set of data paths from each of the plurality of first memory cell arrays to a corresponding DQ pad is physically shorter than each path of a second set of data paths from each of the plurality of second memory cell arrays to the corresponding DQ pad. Each of the plurality of first memory cell arrays is a designated first-speed access cell array and each of the plurality of second memory cell arrays is a designated second-speed access cell array, the second-speed being slower than the first-speed. A size of the each of the plurality of first memory cell arrays is smaller than a size of the each of the plurality of second memory cell arrays.

Abstract translation: 半导体存储器件可以包括多个数据输入/输出DQ焊盘和多个第一和第二存储单元阵列。 从多个第一存储器单元阵列中的每一个到相应的DQ焊盘的第一组数据路径的每个路径物理上比从多个第二存储单元阵列中的每一个到相应的第二组数据路径的第二组数据路径的每个路径短 DQ垫。 多个第一存储单元阵列中的每一个是指定的第一速度存取单元阵列，并且多个第二存储单元阵列中的每一个是指定的第二速度存取单元阵列，第二速度比第一速度慢。 多个第一存储单元阵列中的每一个的大小小于多个第二存储单元阵列中的每一个的大小。