公开(公告)号：US09136130B1

公开(公告)日：2015-09-15

申请号：US14456515

申请日：2014-08-11

申请人： SanDisk Technologies, Inc.

发明人： Takayuki Wada ,  Shigehiro Fujino

IPC分类号： H01L21/336 ,  H01L21/28 ,  H01L27/115

CPC分类号： H01L27/11582 ,  H01L21/31111 ,  H01L21/32134 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

摘要： A method of making a monolithic three dimensional NAND string includes forming a stack of alternating layers of a first material and a second material different from the first material over a substrate, etching the stack to form at least one opening in the stack, forming a buffer layer over a sidewall of the at least one opening, forming a charge storage material layer over the buffer layer, forming a tunnel dielectric layer over the charge storage material layer in the at least one opening, and forming a semiconductor channel material over the tunnel dielectric layer in the at least one opening. The method also includes selectively removing the second material layers without removing the first material layers and etching the buffer layer using the first material layers as a mask to form a plurality of separate discrete buffer segments and to expose portions of the charge storage material layer.

摘要翻译： 制造单片三维NAND串的方法包括在衬底上形成第一材料和不同于第一材料的第二材料的交替层的堆叠，蚀刻堆叠以在堆叠中形成至少一个开口，形成缓冲器 层，在所述至少一个开口的侧壁上，在所述缓冲层上形成电荷存储材料层，在所述至少一个开口中的所述电荷存储材料层上形成隧道介电层，以及在所述隧道电介质上形成半导体沟道材料 在至少一个开口中的层。 该方法还包括在不去除第一材料层的情况下选择性地去除第二材料层，并且使用第一材料层作为掩模蚀刻缓冲层，以形成多个单独的离散缓冲段并暴露电荷存储材料层的部分。

公开(公告)号：US09305849B1

公开(公告)日：2016-04-05

申请号：US14539372

申请日：2014-11-12

申请人： SanDisk Technologies, Inc.

发明人： Masanori Tsutsumi ,  Shigehiro Fujino ,  Sateesh Koka ,  Senaka Kanakamedala ,  Yanli Zhang ,  Raghuveer S. Makala ,  Rahul Sharangpani ,  George Matamis ,  Wei Zhao

IPC分类号： H01L21/76 ,  H01L21/28 ,  H01L21/8239 ,  H01L21/283 ,  H01L27/115 ,  H01L21/822

CPC分类号： H01L21/8239 ,  H01L21/28282 ,  H01L21/8221 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582

摘要： A monolithic three dimensional NAND string includes a semiconductor channel, an end part of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes extending substantially parallel to the major surface of the substrate, a charge storage material layer located between the plurality of control gate electrodes and the semiconductor channel, a tunnel dielectric located between the charge storage material layer and the semiconductor channel, and a blocking dielectric containing a plurality of clam-shaped portions each having two horizontal portions connected by a vertical portion. Each of the plurality of control gate electrodes are located at least partially in an opening in the clam-shaped blocking dielectric, and a plurality of discrete cover oxide segments embedded in part of a thickness of the charge storage material layer and located between the blocking dielectric and the charge storage material layer.

摘要翻译： 单片三维NAND串包括半导体通道，半导体通道的基本垂直于基板的主表面延伸的端部，基本上平行于基板的主表面延伸的多个控制栅电极，电荷存储材料 位于多个控制栅电极和半导体沟道之间的层，位于电荷存储材料层和半导体沟道之间的隧道电介质，以及包含多个蛤状部分的阻挡电介质，每个具有两个水平部分的垂直部分 一部分。 多个控制栅电极中的每一个至少部分地位于蛤状阻挡电介质中的开口中，以及多个分立的覆盖氧化物段，其嵌入部分电荷存储材料层的厚度并位于阻挡电介质 和电荷存储材料层。

公开(公告)号：US09548313B2

公开(公告)日：2017-01-17

申请号：US14725466

申请日：2015-05-29

申请人： SanDisk Technologies, Inc.

发明人： Shinsuke Yada ,  Shigehiro Fujino ,  Hajime Kimura ,  Masanori Terahara ,  Ryoichi Honma ,  Hiroyuki Ogawa ,  Ryousuke Itou

IPC分类号： H01L21/336 ,  H01L27/115

CPC分类号： H01L27/11556 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582

摘要： A method of making a monolithic three dimensional NAND string includes forming a select gate layer of a third material over a major surface of a substrate, forming a stack of alternating first material and second material layers over the select gate layer, where the first material, the second material and the third material are different from each other, and etching the stack using a first etch chemistry to form at least one opening in the stack at least to the select gate layer, such that the select gate layer acts as an etch stop layer during the step of etching.

摘要翻译： 制造单片三维NAND串的方法包括在衬底的主表面上形成第三材料的选择栅极层，在选择栅极层上形成交替的第一材料和第二材料层的堆叠，其中第一材料， 所述第二材料和所述第三材料彼此不同，并且使用第一蚀刻化学法蚀刻所述堆叠，以在所述堆叠中至少形成至少一个所述选择栅极层的开口，使得所述选择栅极层用作蚀刻停止 在蚀刻步骤期间。

公开(公告)号：US09305934B1

公开(公告)日：2016-04-05

申请号：US14517134

申请日：2014-10-17

申请人： SanDisk Technologies, Inc.

发明人： Hao Ding ,  Masahiro Yaegashi ,  Shigehiro Fujino ,  Shuji Minagawa ,  Yuji Fukano

IPC分类号： H01L21/00 ,  H01L27/00 ,  H01L27/115 ,  H01L29/423 ,  H01L21/306 ,  H01L21/02 ,  H01L21/28 ,  H01L23/532

CPC分类号： H01L27/11573 ,  H01L23/53266 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

摘要： A multilevel structure includes a stack of an alternating plurality of electrically conductive layers and insulator layers located over a semiconductor substrate, and an array of memory stack structures located within memory openings through the stack. An epitaxial semiconductor pedestal is provided, which is in epitaxial alignment with a single crystalline substrate semiconductor material in the semiconductor substrate and has a top surface within a horizontal plane located above a plurality of electrically conductive layers within the stack. The contact via structures for the semiconductor devices on the epitaxial semiconductor pedestal can extend can be less than the thickness of the stack.

摘要翻译： 多级结构包括交替的多个导电层和位于半导体衬底之上的绝缘体层的堆叠，以及位于通过堆叠的存储器开口内的存储器堆叠结构的阵列。 提供外延半导体基座，其与半导体衬底中的单晶衬底半导体材料外延对准，并且在位于堆叠内的多个导电层上方的水平面内具有顶表面。 在外延半导体基座上的半导体器件的接触通孔结构可以延伸可以小于堆叠的厚度。