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12 条记录 (耗时 0.016 秒)

    Batch contacts for multiple electrically conductive layers
    1.
    发明授权
    Batch contacts for multiple electrically conductive layers 有权
    用于多个导电层的批次触点

    公开(公告)号：US09530787B2

    公开(公告)日：2016-12-27

    申请号：US14518430

    申请日：2014-10-20

    申请人： SanDisk Technologies, Inc.

    发明人： Masanori Tsutsumi ,  Naoki Ihata ,  Shinsuke Yada ,  Ryoichi Honma

    IPC分类号： H01L29/792 ,  H01L27/115 ,  H01L21/768

    CPC分类号： H01L27/11582 ,  H01L21/76802 ,  H01L21/76877 ,  H01L27/1157 ,  H01L27/11575

    摘要： A stepped structure is formed on a stack of an alternating plurality of insulator layers and material layers such that at least two material layers have vertically coincident sidewalls. In one embodiment, the material layers can be electrically conductive layers, and a contact via structure can contact the vertically coincident sidewalls. In another embodiment, a sacrificial spacer can be formed on the vertically coincident sidewalls, and the material layers and the sacrificial spacer can be replaced with a conductive material. A contact via structure can be formed on a set of layers electrically shorted by a vertical conductive material portion that is formed in a volume of the spacer. The contact via structure can provide electrical contact to multiple electrically conductive layers.

    摘要翻译： 梯形结构形成在交替的多个绝缘体层和材料层的堆叠上，使得至少两个材料层具有垂直重合的侧壁。 在一个实施例中，材料层可以是导电层，并且接触通孔结构可以接触垂直重合的侧壁。 在另一个实施例中，可以在垂直重合的侧壁上形成牺牲隔离物，并且可以用导电材料代替材料层和牺牲隔离物。 接触通孔结构可以形成在由形成在间隔物的体积中的垂直导电材料部分电短路的一组层上。 接触通孔结构可以提供与多个导电层的电接触。

    BATCH CONTACTS FOR MULTIPLE ELECTRICALLY CONDUCTIVE LAYERS
    3.
    发明申请
    BATCH CONTACTS FOR MULTIPLE ELECTRICALLY CONDUCTIVE LAYERS 有权
    批量接触多个电导电层

    公开(公告)号：US20160111438A1

    公开(公告)日：2016-04-21

    申请号：US14518430

    申请日：2014-10-20

    申请人： SanDisk Technologies, Inc.

    发明人： Masanori TSUTSUMI ,  Naoki Ihata ,  Shinsuke Yada ,  Ryoichi Honma

    IPC分类号： H01L27/115 ,  H01L29/423 ,  H01L21/768 ,  H01L21/28 ,  H01L23/522 ,  H01L23/528

    CPC分类号： H01L27/11582 ,  H01L21/76802 ,  H01L21/76877 ,  H01L27/1157 ,  H01L27/11575

    摘要： A stepped structure is formed on a stack of an alternating plurality of insulator layers and material layers such that at least two material layers have vertically coincident sidewalls. In one embodiment, the material layers can be electrically conductive layers, and a contact via structure can contact the vertically coincident sidewalls. In another embodiment, a sacrificial spacer can be formed on the vertically coincident sidewalls, and the material layers and the sacrificial spacer can be replaced with a conductive material. A contact via structure can be formed on a set of layers electrically shorted by a vertical conductive material portion that is formed in a volume of the spacer. The contact via structure can provide electrical contact to multiple electrically conductive layers.

    摘要翻译： 梯形结构形成在交替的多个绝缘体层和材料层的堆叠上，使得至少两个材料层具有垂直重合的侧壁。 在一个实施例中，材料层可以是导电层，并且接触通孔结构可以接触垂直重合的侧壁。 在另一个实施例中，可以在垂直重合的侧壁上形成牺牲隔离物，并且可以用导电材料代替材料层和牺牲隔离物。 接触通孔结构可以形成在由形成在间隔物的体积中的垂直导电材料部分电短路的一组层上。 接触通孔结构可以提供与多个导电层的电接触。

    Honeycomb cell structure three-dimensional non-volatile memory device
    4.
    发明授权
    Honeycomb cell structure three-dimensional non-volatile memory device 有权

    公开(公告)号：US09812461B2

    公开(公告)日：2017-11-07

    申请号：US14660023

    申请日：2015-03-17

    申请人： SANDISK TECHNOLOGIES INC.

    发明人： Yasushi Doda ,  Ryoichi Honma

    IPC分类号： H01L29/792 ,  H01L27/11582 ,  H01L27/11565 ,  H01L29/51 ,  H01L27/1157

    CPC分类号： H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/513

    摘要： A monolithic three-dimensional memory device includes a plurality of memory stack structures arranged in a hexagonal lattice and located over a substrate. The hexagonal lattice structure is defined by hexagons each having a pair of sides that are parallel to a first horizontal direction and perpendicular to a second horizontal direction, the memory stack structures are located at vertices of the hexagonal lattice, and each memory stack structure includes vertically spaced memory elements and a vertical semiconductor channel. Source contact via structures are located at each center of a subset of the hexagons that forms a one-dimensional array that extends along the second horizontal direction, each source contact via structure being electrically shorted to a respective source region over, or within, the substrate.

    Metallic etch stop layer in a three-dimensional memory structure
    5.
    发明授权
    Metallic etch stop layer in a three-dimensional memory structure 有权
    金属蚀刻停止层在三维记忆结构中

    公开(公告)号：US09530788B2

    公开(公告)日：2016-12-27

    申请号：US14659963

    申请日：2015-03-17

    申请人： SANDISK TECHNOLOGIES INC.

    发明人： Tomohiro Oginoe ,  Ryoichi Honma ,  Masanori Terahara

    IPC分类号： H01L27/115 ,  H01L29/792 ,  H01L23/522 ,  H01L29/51 ,  H01L29/49 ,  H01L29/788 ,  H01L29/16 ,  H01L29/423 ,  H01L21/768 ,  H01L21/28 ,  H01L29/66 ,  H01L23/528

    CPC分类号： H01L27/11582 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11575 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

    摘要： A dielectric liner, a bottom conductive layer, and a stack of alternating layers including insulator layers and spacer material layers are sequentially formed over a substrate. A memory opening extending through the stack can be formed by an anisotropic etch process that employs the bottom conductive layer as an etch stop layer. The memory opening is extended downward by etching through the bottom conductive layer and the dielectric liner, while minimizing an overetch into the substrate. A memory stack structure can be formed in the memory opening. Subsequently, a backside contact trench can be formed through the stack employing the bottom conductive layer as an etch stop layer. The spacer material layers can be removed to form backside recesses, which are filled with a conductive material to form electrically conductive layers. The remaining portion of the bottom conductive layer can be employed as a source select gate electrode.

    摘要翻译： 电介质衬垫，底部导电层和包括绝缘体层和间隔物材料层的交替层的叠层依次形成在衬底上。 延伸穿过堆叠的存储器开口可以通过使用底部导电层作为蚀刻停止层的各向异性蚀刻工艺形成。 通过蚀刻穿过底部导电层和电介质衬垫向下延伸存储器开口，同时最小化进入衬底的过蚀刻。 存储器堆叠结构可以形成在存储器开口中。 随后，可以通过使用底部导电层作为蚀刻停止层的堆叠形成背面接触沟槽。 间隔材料层可以被去除以形成背面凹槽，其中填充有导电材料以形成导电层。 底部导电层的剩余部分可以用作源选择栅电极。

    Self-aligned integrated line and via structure for a three-dimensional semiconductor device
    7.
    发明授权
    Self-aligned integrated line and via structure for a three-dimensional semiconductor device 有权
    用于三维半导体器件的自对准集成线和通孔结构

    公开(公告)号：US09484296B2

    公开(公告)日：2016-11-01

    申请号：US14620593

    申请日：2015-02-12

    申请人： SANDISK TECHNOLOGIES INC.

    发明人： Akihide Takahashi ,  Ryoichi Honma

    IPC分类号： H01L23/522 ,  H01L23/528 ,  H01L23/535 ,  H01L21/768 ,  H01L27/115

    CPC分类号： H01L23/5226 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76829 ,  H01L21/76843 ,  H01L21/76847 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/5283 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11582

    摘要： At least one via level dielectric layer and at least one line level dielectric layer are sequentially formed over an array of device structures. Conductive line structures are formed within the at least one line level dielectric layer. A mask layer is applied over the conductive line structures, and is lithographically patterned to form opening therein. Portions of the conductive line structures are removed from underneath the openings in the patterned mask layer to form via cavities. The via cavities are vertically extended through the at least one via level dielectric layer employing a combination of the mask layer and the at least one line level dielectric layer as an etch mask. At least one conductive material can be deposited in the via cavities to form conductive via structures, which, in conjunction with the conductive line structures, constitute integrated line and via structures.

    摘要翻译： 在器件结构的阵列上依次形成至少一个通孔级介电层和至少一个线级介质层。 导电线结构形成在至少一个线级介质层内。 将掩模层施加在导电线结构上，并且被光刻图案化以在其中形成开口。 导电线结构的部分从图案化掩模层中的开口下方移除以形成通孔。 使用掩模层和至少一个线级介质层的组合作为蚀刻掩模，将通孔腔垂直延伸穿过至少一个通孔级介质层。 至少一个导电材料可以沉积在通孔腔中以形成导电通孔结构，其结合导电线结构构成集成线路和通孔结构。