公开(公告)号：US09760307B2

公开(公告)日：2017-09-12

申请号：US14861953

申请日：2015-09-22

Applicant: SanDisk Technologies LLC

Inventor： Chris Avila ,  Yingda Dong ,  Alexander Kwok-Tung Mak ,  Steven T. Sprouse

IPC: G11C16/04 ,  G06F3/06 ,  G06F11/10

CPC classification number: G06F3/0652 ,  G06F3/0619 ,  G06F3/0679 ,  G06F11/106 ,  G11C16/04

Abstract: An array of non-volatile memory cells includes a first plurality of nonvolatile memory cells and a second plurality of non-volatile memory cells. The first plurality of memory cells, which have first diameters of memory holes, are assigned to store portions of data that are not frequently read. The second plurality of memory cells, which have second diameters of memory holes, are assigned to store portions of data that are frequently read. The first diameters are smaller than the second diameters.

公开(公告)号：US10684794B2

公开(公告)日：2020-06-16

申请号：US15648415

申请日：2017-07-12

Applicant: SanDisk Technologies LLC

Inventor： Reed P. Tidwell ,  Steven T. Sprouse ,  Satish B. Vasudeva ,  James M. Higgins ,  Jonathan Q. Tu

IPC: G06F3/06 ,  G06F1/3234 ,  G06F1/28 ,  G06F1/3206

Abstract: In a memory system having a storage controller and a plurality of distinct sets of non-volatile memory devices, each respective channel controller of a plurality of channel controllers, each channel controller corresponding to a distinct set of the plurality of distinct sets of non-volatile memory devices, determines a backlog of the respective channel controller in accordance with pending commands in one or more command queues, receives power credits allocated by the storage controller, based at least in part on the backlog of the respective channel controller, and while executing commands in the one or more command queues, limits execution of said commands in accordance with the received power credits. For example, limiting execution includes deferring execution of a respective command in accordance with a determination that executing the respective command would require power credits in excess of power credits available in the respective channel controller.

公开(公告)号：US10509591B2

公开(公告)日：2019-12-17

申请号：US15648417

申请日：2017-07-12

Applicant: SanDisk Technologies LLC

Inventor： Reed P. Tidwell ,  Steven T. Sprouse ,  Satish B. Vasudeva ,  James M. Higgins ,  Jonathan Q. Tu

IPC: G06F3/06 ,  G06F1/28

Abstract: In a memory system having a storage controller and a plurality of distinct sets of non-volatile memory devices, each respective channel controller of a plurality of channel controllers, each channel controller corresponding to a distinct set of the plurality of distinct sets of non-volatile memory devices, receives power credits allocated by the storage controller, including an average power credit and a peak power credit; and while executing commands in the one or more command queues, limits execution of said commands in accordance with the received average power credit and the received peak power credit. In some embodiments, a total number of average power credits allocated by the storage controller is variable and a total number of peak power credits allocated by the storage controller is fixed.

公开(公告)号：US20180335978A1

公开(公告)日：2018-11-22

申请号：US15648417

申请日：2017-07-12

Applicant: SanDisk Technologies LLC

Inventor： Reed P. Tidwell ,  Steven T. Sprouse ,  Satish B. Vasudeva ,  James M. Higgins ,  Jonathan Q. Tu

IPC: G06F3/06 ,  G06F1/28

Abstract: In a memory system having a storage controller and a plurality of distinct sets of non-volatile memory devices, each respective channel controller of a plurality of channel controllers, each channel controller corresponding to a distinct set of the plurality of distinct sets of non-volatile memory devices, receives power credits allocated by the storage controller, including an average power credit and a peak power credit; and while executing commands in the one or more command queues, limits execution of said commands in accordance with the received average power credit and the received peak power credit. In some embodiments, a total number of average power credits allocated by the storage controller is variable and a total number of peak power credits allocated by the storage controller is fixed.

公开(公告)号：US09768808B2

公开(公告)日：2017-09-19

申请号：US14885883

申请日：2015-10-16

Applicant: SanDisk Technologies LLC

Inventor： Steven T. Sprouse ,  Aaron K. Olbrich ,  James Fitzpatrick ,  Neil R. Darragh

IPC: G11C29/00 ,  H03M13/35 ,  G11C29/52 ,  H03M13/00 ,  G06F11/10 ,  G11C29/02 ,  G11C29/04

CPC classification number: H03M13/353 ,  G06F11/1048 ,  G11C29/028 ,  G11C29/52 ,  G11C2029/0411 ,  H03M13/6356 ,  H03M13/6362 ,  H03M13/6513

Abstract: The various implementations described herein include systems, methods and/or devices for modifying an error correction format of a respective memory portion of non-volatile memory in a storage device. In one aspect, the method includes, for respective memory portions of the non-volatile memory, obtaining a performance metric of the respective memory portion, and modifying a current error correction format in accordance with the measured performance metric, the current error correction format corresponding to a code rate, codeword structure, and error correction type. Furthermore, data is stored, and errors are detected and corrected, in the respective memory portion in accordance with the modified error correction format. The current and modified error correction formats are distinct, and comprise two of a sequence of predefined error correction formats, wherein a plurality of the sequence of predefined error correction formats have a same number of error correction bits and different numbers of data bits.

公开(公告)号：US20180335977A1

公开(公告)日：2018-11-22

申请号：US15648415

申请日：2017-07-12

Applicant: SanDisk Technologies LLC

Inventor： Reed P. Tidwell ,  Steven T. Sprouse ,  Satish B. Vasudeva ,  James M. Higgins ,  Jonathan Q. Tu

IPC: G06F3/06 ,  G06F1/28

Abstract: In a memory system having a storage controller and a plurality of distinct sets of non-volatile memory devices, each respective channel controller of a plurality of channel controllers, each channel controller corresponding to a distinct set of the plurality of distinct sets of non-volatile memory devices, determines a backlog of the respective channel controller in accordance with pending commands in one or more command queues, receives power credits allocated by the storage controller, based at least in part on the backlog of the respective channel controller, and while executing commands in the one or more command queues, limits execution of said commands in accordance with the received power credits. For example, limiting execution includes deferring execution of a respective command in accordance with a determination that executing the respective command would require power credits in excess of power credits available in the respective channel controller.

公开(公告)号：US10127150B2

公开(公告)日：2018-11-13

申请号：US13749523

申请日：2013-01-24

Applicant: SanDisk Technologies LLC

Inventor： Steven T. Sprouse ,  Yan Li

IPC: G06F12/00 ,  G06F12/02 ,  G11C11/56 ,  G11C15/04 ,  G11C16/04 ,  G11C16/34 ,  G11C16/02

Abstract: A NAND Flash based content addressable memory (CAM) is used for a key-value addressed storage drive. The device can use a standard transport protocol such as PCI-E, SAS, SATA, eMMC, SCSI, and so on. A host writes a key-value pair to the drive, where the drive writes the keys along bit lines of a CAM NAND portion of the drive and stores the value in the drive. The drive then maintains a table linking the keys to location of the value. In a read process, the host provides a key to drive, which then broadcasts down the word lines of blocks storing the keys. Based on any matching bit lines, the tables can then be used to retrieve and supply the corresponding data to the host.