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公开(公告)号:US11256567B2
公开(公告)日:2022-02-22
申请号:US16907669
申请日:2020-06-22
Applicant: SanDisk Technologies LLC
Inventor: Mostafa El Gamal , James Fitzpatrick
Abstract: An apparatus includes memory cells programmed to one of a plurality of data states, wherein the memory cells are configured such that the plurality of data states comprise an error-prone data state. Sense circuitry of the apparatus is configured to sense first memory cells programmed to the error-prone data state, determine a bit encoding for the first memory cells, sense other memory cells programmed to other data states, and determine a bit encoding for the other memory cells. A communication circuit of the apparatus is configured to communicate the bit encoding for the other memory cells, the bit encoding for the first memory cells, and an indication that the first memory cells are programmed to the error-prone data state, in response to a single read command from a controller.
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公开(公告)号:US10228990B2
公开(公告)日:2019-03-12
申请号:US15195910
申请日:2016-06-28
Applicant: SanDisk Technologies LLC
Inventor: Yiwei Song , Nian Niles Yang , James Fitzpatrick
Abstract: Systems, methods and/or devices are used to adjust error metrics for a memory portion of non-volatile memory in a storage device. In one aspect, a first write and a first read are performed on the memory portion. In accordance with results of the first read, a first error metric value for the memory portion is determined. In accordance with a determination that the first error metric value exceeds a first threshold value, an entry for the memory portion is added to a table. After the first write, when a second write to the memory portion is performed, it is determined whether the entry for the memory portion is present in the table. In accordance with a determination that the entry for the memory portion is present in the table, the second write uses a first error adjustment characteristic that is determined in accordance with the first error metric value.
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公开(公告)号:US20170371559A1
公开(公告)日:2017-12-28
申请号:US15195940
申请日:2016-06-28
Applicant: SanDisk Technologies LLC
Inventor: James M. Higgins , James Fitzpatrick
IPC: G06F3/06
CPC classification number: G06F3/0611 , G06F3/0653 , G06F3/0673 , G06F12/0246 , G06F12/0871 , G06F2212/1016 , G06F2212/217 , G06F2212/222 , G06F2212/6042 , G06F2212/7202 , G06F2212/7208
Abstract: The various embodiments described herein include methods, systems, and devices for optimizing media read times. In one aspect, a method is performed at a device at a storage device with one or more processors and memory coupled to the one or more processors. The method includes: (i) predicting a read frequency for particular data; (ii) based on the predicted read frequency, determining one or more preferred storage locations within the memory; and (iii) storing the particular data in a preferred storage location of the one or more preferred storage locations.
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公开(公告)号:US20170084346A1
公开(公告)日:2017-03-23
申请号:US15276635
申请日:2016-09-26
Applicant: SanDisk Technologies LLC
Inventor: Niles Yang , Jiahui Yuan , James Fitzpatrick
CPC classification number: G11C11/5635 , G11C7/04 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0023 , G11C13/0026 , G11C13/0033 , G11C13/0097 , G11C13/025 , G11C16/0466 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C16/3409 , G11C29/025 , G11C29/028 , G11C29/44 , G11C29/76 , G11C29/88 , G11C2029/0411 , G11C2029/1202 , G11C2029/1204 , G11C2213/71
Abstract: A three dimensional nonvolatile memory system includes a sensing unit configured to sense bit line current and/or voltage for bit lines of a plurality of separately-selectable portions of a block and to compare respective results with a reference and an adjustment unit configured to individually modify operating parameters for one or more of the plurality of separately-selectable portions in response to the comparing of respective results with the reference.
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5.
公开(公告)号:US20160364155A1
公开(公告)日:2016-12-15
申请号:US15249237
申请日:2016-08-26
Applicant: SanDisk Technologies LLC
Inventor: James Fitzpatrick , Mark Dancho , James M. Higgins , Robert W. Ellis , Bernardo Rub
IPC: G06F3/06
CPC classification number: G06F3/0616 , G06F3/0631 , G06F3/064 , G06F3/0679 , G11C11/5635 , G11C16/10 , G11C16/16 , G11C16/3495
Abstract: Systems, methods and/or devices are used to enable dynamic erase block grouping. In one aspect, the method includes (1) maintaining metadata for each erase block of a plurality of erase blocks in a data storage system, wherein a respective metadata for a respective erase block includes one or more characteristics of the respective erase block, (2) allocating a set of erase blocks, of the plurality of erase blocks, as unassociated erase blocks, (3) selecting two or more unassociated erase blocks in accordance with characteristics of the unassociated erase blocks so as to select unassociated erase blocks with similar characteristics, and (4) grouping the two or more unassociated erase blocks with similar characteristics to form a super block.
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公开(公告)号:US09768808B2
公开(公告)日:2017-09-19
申请号:US14885883
申请日:2015-10-16
Applicant: SanDisk Technologies LLC
Inventor: Steven T. Sprouse , Aaron K. Olbrich , James Fitzpatrick , Neil R. Darragh
CPC classification number: H03M13/353 , G06F11/1048 , G11C29/028 , G11C29/52 , G11C2029/0411 , H03M13/6356 , H03M13/6362 , H03M13/6513
Abstract: The various implementations described herein include systems, methods and/or devices for modifying an error correction format of a respective memory portion of non-volatile memory in a storage device. In one aspect, the method includes, for respective memory portions of the non-volatile memory, obtaining a performance metric of the respective memory portion, and modifying a current error correction format in accordance with the measured performance metric, the current error correction format corresponding to a code rate, codeword structure, and error correction type. Furthermore, data is stored, and errors are detected and corrected, in the respective memory portion in accordance with the modified error correction format. The current and modified error correction formats are distinct, and comprise two of a sequence of predefined error correction formats, wherein a plurality of the sequence of predefined error correction formats have a same number of error correction bits and different numbers of data bits.
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公开(公告)号:US09691473B2
公开(公告)日:2017-06-27
申请号:US15276635
申请日:2016-09-26
Applicant: SanDisk Technologies LLC
Inventor: Niles Yang , Jiahui Yuan , James Fitzpatrick
CPC classification number: G11C11/5635 , G11C7/04 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0023 , G11C13/0026 , G11C13/0033 , G11C13/0097 , G11C13/025 , G11C16/0466 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C16/3409 , G11C29/025 , G11C29/028 , G11C29/44 , G11C29/76 , G11C29/88 , G11C2029/0411 , G11C2029/1202 , G11C2029/1204 , G11C2213/71
Abstract: A three dimensional nonvolatile memory system includes a sensing unit configured to sense bit line current and/or voltage for bit lines of a plurality of separately-selectable portions of a block and to compare respective results with a reference and an adjustment unit configured to individually modify operating parameters for one or more of the plurality of separately-selectable portions in response to the comparing of respective results with the reference.
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8.
公开(公告)号:US09665295B2
公开(公告)日:2017-05-30
申请号:US15249237
申请日:2016-08-26
Applicant: SanDisk Technologies LLC
Inventor: James Fitzpatrick , Mark Dancho , James M. Higgins , Robert W. Ellis , Bernardo Rub
CPC classification number: G06F3/0616 , G06F3/0631 , G06F3/064 , G06F3/0679 , G11C11/5635 , G11C16/10 , G11C16/16 , G11C16/3495
Abstract: Systems, methods and/or devices are used to enable dynamic erase block grouping. In one aspect, the method includes (1) maintaining metadata for each erase block of a plurality of erase blocks in a data storage system, wherein a respective metadata for a respective erase block includes one or more characteristics of the respective erase block, (2) allocating a set of erase blocks, of the plurality of erase blocks, as unassociated erase blocks, (3) selecting two or more unassociated erase blocks in accordance with characteristics of the unassociated erase blocks so as to select unassociated erase blocks with similar characteristics, and (4) grouping the two or more unassociated erase blocks with similar characteristics to form a super block.
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公开(公告)号:US20170084342A1
公开(公告)日:2017-03-23
申请号:US15190749
申请日:2016-06-23
Applicant: SanDisk Technologies LLC
Inventor: Niles Yang , James Fitzpatrick , Jiahui Yuan
CPC classification number: G11C16/16 , G11C16/0483 , G11C16/26 , G11C29/025 , G11C29/028 , G11C29/70 , G11C29/88 , G11C2029/0411 , G11C2029/1202 , G11C2029/1204
Abstract: In a nonvolatile memory block that contains separately-selectable sets of NAND strings, a bit line current sensing unit is configured to sense bit line current for a separately-selectable set of NAND strings of the block. A bit line voltage adjustment unit is configured to apply a first and second bit line voltages to separately-selectable sets of NAND strings that have bit line currents greater and less than the minimum current respectively, the second bit line voltage being greater than the first bit line voltage.
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公开(公告)号:US20170139761A1
公开(公告)日:2017-05-18
申请号:US15195910
申请日:2016-06-28
Applicant: SanDisk Technologies LLC
Inventor: Yiwei Song , Nian Niles Yang , James Fitzpatrick
IPC: G06F11/07
CPC classification number: G06F11/073 , G06F11/0754 , G06F11/076 , G06F11/1072 , G06F12/02 , G11C16/349 , G11C29/4401 , G11C2029/0409 , G11C2029/0411
Abstract: Systems, methods and/or devices are used to adjust error metrics for a memory portion of non-volatile memory in a storage device. In one aspect, a first write and a first read are performed on the memory portion. In accordance with results of the first read, a first error metric value for the memory portion is determined. In accordance with a determination that the first error metric value exceeds a first threshold value, an entry for the memory portion is added to a table. After the first write, when a second write to the memory portion is performed, it is determined whether the entry for the memory portion is present in the table. In accordance with a determination that the entry for the memory portion is present in the table, the second write uses a first error adjustment characteristic that is determined in accordance with the first error metric value.
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