公开(公告)号：US20060205742A1

公开(公告)日：2006-09-14

申请号：US11433416

申请日：2006-05-15

申请人： Seiichiro Kawashima ,  Toshiyuki Matsuno ,  Naoki Fukuda ,  Kenichi Saitoh ,  Yoshimasa Yamaguchi ,  Masaya Higashi

发明人： Seiichiro Kawashima ,  Toshiyuki Matsuno ,  Naoki Fukuda ,  Kenichi Saitoh ,  Yoshimasa Yamaguchi ,  Masaya Higashi

IPC分类号： A61K31/519 ,  C07D498/02 ,  C07D487/04 ,  C07D471/04 ,  A61K31/4745 ,  A61K31/43

CPC分类号： C07D471/04 ,  C07D487/04 ,  C07D513/04

摘要： Heterocyclic compound represented by the formula I wherein represents or the like; R1 represents hydrogen atom, C1-C6 alkyl or benzyloxy; R2 represents methyl or nil; R3 represents hydrogen atom, C1-C6 alkyl, C2-C6 alkenyl, C3-C8 cycloalkyl or —CH2R5 [wherein R5 represents phenyl (which may be substituted with C1-C6 alkyl, halogen atom or cyano)] or thienyl; R4 represents C1-C6 alkyl, C2-C6 alkenyl, C3-C8 cycloalkyl or —CH2R6 [wherein R6 represents phenyl (which may be substituted with C1-C6alkyl, halogen atom or cyano), naphtyl or thienyl]; or R3 is coupled with R4.

摘要翻译： 由式I表示的杂环化合物，其中表示等; R 1表示氢原子，C 1 -C 6烷基或苄氧基; R 2表示甲基或无; R 3表示氢原子，C 1 -C 6烷基，C 2 -C 6烷基，C 1 -C 6烷基，C 1 -C 6烷基， / SUB-烯基，C 3 -C 8环烷基或-CH 2 R 5 [其中R _{5代表苯基（其可以被C 1 -C 6烷基，卤素原子或氰基）]或噻吩基取代; R 4代表C 1 -C 6烷基，C 2 -C 6烷基，C 2 -C 6烷基，C 2 -C 6烷基，C 2 -C 6烷基， 烯基，C 3 -C 8环烷基或-CH 2 R 6 [其中R 6' / SUB表示苯基（其可以被C 1 -C 6烷基，卤素原子或氰基取代），萘基或噻吩基]; 或R 3与R 4连接。}

公开(公告)号：US07767824B2

公开(公告)日：2010-08-03

申请号：US11433416

申请日：2006-05-15

申请人： Seiichiro Kawashima ,  Toshiyuki Matsuno ,  Naoki Fukuda ,  Kenichi Saitoh ,  Yoshimasa Yamaguchi ,  Masaya Higashi

发明人： Seiichiro Kawashima ,  Toshiyuki Matsuno ,  Naoki Fukuda ,  Kenichi Saitoh ,  Yoshimasa Yamaguchi ,  Masaya Higashi

IPC分类号： C07D513/04 ,  A61K31/429

CPC分类号： C07D471/04 ,  C07D487/04 ,  C07D513/04

摘要： Heterocyclic compound represented by the formula I wherein represents or the like; R1 represents hydrogen atom, C1-C6 alkyl or benzyloxy; R2 represents methyl or nil; R3 represents hydrogen atom, C1-C6 alkyl, C2-C6 alkenyl, C3-C8 cycloalkyl or —CH2R5 [wherein R5 represents phenyl (which may be substituted with C1-C6 alkyl, halogen atom or cyano)] or thienyl; R4 represents C1-C6 alkyl, C2-C6 alkenyl, C3-C8 cycloalkyl or —CH2R6 [wherein R6 represents phenyl (which may be substituted with C1-C6alkyl, halogen atom or cyano), naphtyl or thienyl]; or R3 is coupled with R4.

摘要翻译： 由式I表示的杂环化合物，其中表示等; R1表示氢原子，C1-C6烷基或苄氧基; R2表示甲基或无; R 3表示氢原子，C 1 -C 6烷基，C 2 -C 6烯基，C 3 -C 8环烷基或-CH 2 R 5 [其中R 5表示苯基（其可以被C 1 -C 6烷基，卤素原子或氰基取代）]或噻吩基; R 4表示C 1 -C 6烷基，C 2 -C 6烯基，C 3 -C 8环烷基或-CH 2 R 6 [其中R 6表示苯基（其可以被C 1 -C 6烷基，卤素原子或氰基取代），萘基或噻吩基]。 或R3与R4结合。

公开(公告)号：US06635652B1

公开(公告)日：2003-10-21

申请号：US10030159

申请日：2002-01-30

申请人： Seiichiro Kawashima ,  Toshiyuki Matsuno ,  Naoki Fukuda ,  Kenichi Saitoh ,  Yoshimasa Yamaguchi ,  Masaya Higashi

发明人： Seiichiro Kawashima ,  Toshiyuki Matsuno ,  Naoki Fukuda ,  Kenichi Saitoh ,  Yoshimasa Yamaguchi ,  Masaya Higashi

IPC分类号： A61K31437

CPC分类号： C07D471/04

摘要： Azaindolizinon derivatives or pharmaceutically acceptable salts thereof represented by the formula I: wherein R1 represents hydrogen atom, halogen atom or C1-C6 alkyl, R2 represents hydrogen atom, C1-C6 alkyl, C1-C6alkoxy, hydroxy, halogen atom, amino, acetylamino, benzylamino, trifluoromethyl or —O—(CH2)n—R5 (R5 represents vinyl, C3-C8 cycloalkyl or phenyl, n being 0 or 1), R3 and R4 respectively represent C1-C6 alkyl or —CH(R7)—R6 (wherein R6 represents vinyl, ethynyl, phenyl (which may be substituted with C1-C6 alkyl, C1-C6 alkoxy, hydroxy, one or two halogen atoms, di C1-C6 alkylamino, cyano, nitro, carboxy or phenyl), phenethyl, pyridyl, thienyl or furyl and R7 represents hydrogen atom or C1-C6 alkyl) or R3 is coupled with R4 to form indan or dihydrophenalene.

摘要翻译： 由式I表示的吖草酮衍生物或其药学上可接受的盐：其中R1表示氢原子，卤素原子或C1-C6烷基，R2表示氢原子，C1-C6烷基，C1-C6烷氧基，羟基，卤素原子，氨基，乙酰氨基， 苄基氨基，三氟甲基或-O-（CH 2）n -R 5（R 5表示乙烯基，C 3 -C 8环烷基或苯基，n为0或1），R 3和R 4分别表示C 1 -C 6烷基或-CH（R 7） 其中R 6表示乙烯基，乙炔基，苯基（其可以被C 1 -C 6烷基，C 1 -C 6烷氧基，羟基，一个或两个卤素原子，二C 1 -C 6烷基氨基，氰基，硝基，羧基或苯基）取代，苯乙基，吡啶基 ，噻吩基或呋喃基，R 7表示氢原子或C 1 -C 6烷基）或R 3与R 4一起形成茚满或二氢苯并噻吩。

公开(公告)号：US07141579B2

公开(公告)日：2006-11-28

申请号：US10466321

申请日：2002-01-30

申请人： Seiichiro Kawashima ,  Toshiyuki Matsuno ,  Naoki Fukuda ,  Kenichi Saitoh ,  Yoshimasa Yamaguchi ,  Masaya Higashi

发明人： Seiichiro Kawashima ,  Toshiyuki Matsuno ,  Naoki Fukuda ,  Kenichi Saitoh ,  Yoshimasa Yamaguchi ,  Masaya Higashi

IPC分类号： A61K31/44 ,  C07D471/04 ,  C07D471/10

CPC分类号： C07D471/04 ,  C07D487/04 ,  C07D513/04

摘要： Heterocyclic compound represented by the formula I wherein represents or the like; R1 represents hydrogen atom, C1–C6 alkyl or benzyloxy; R2 represents methyl or nil; R3 represents hydrogen atom, C1–C6 alkyl, C2–C6 alkenyl, C3–C8 cycloalkyl or —CH2R5 [wherein R5 represents phenyl (which may be substituted with C1–C6 alkyl, halogen atom or cyano)] or thienyl; R4 represents C1–C6 alkyl, C2–C6 alkenyl, C3–C8 cycloalkyl or —CH2R6 [wherein R6 represents phenyl (which may be substituted with C1–C6 alkyl, halogen atom or cyano), naphtyl or thienyl]; or R3 is coupled with R4.

摘要翻译： 由式I表示的杂环化合物，其中表示等; R 1表示氢原子，C 1 -C 6烷基或苄氧基; R 2表示甲基或无; R 3表示氢原子，C 1 -C 6烷基，C 2 -C 6烷基，C 1 -C 6烷基，C 1 -C 6烷基， / SUB-烯基，C 3 -C 8环烷基或-CH 2 R 5 [其中R _{5代表苯基（其可以被C 1 -C 6烷基，卤素原子或氰基）]或噻吩基取代; R 4代表C 1 -C 6烷基，C 2 -C 6烷基，C 2 -C 6烷基，C 2 -C 6烷基，C 2 -C 6烷基， 烯基，C 3 -C 8环烷基或-CH 2 R 6 [其中R 6' / SUB表示苯基（其可以被C 1 -C 6烷基，卤素原子或氰基取代），萘基或噻吩基]; 或R 3与R 4连接。}

公开(公告)号：US08248629B2

公开(公告)日：2012-08-21

申请号：US12215020

申请日：2008-06-23

申请人： Naoki Fukuda

发明人： Naoki Fukuda

IPC分类号： G06K15/00

CPC分类号： G06F3/1285 ,  G03G15/5004 ,  G03G15/5087 ,  G03G2215/00126 ,  G06F3/1204 ,  G06F3/1208 ,  G06F3/1263

摘要： A job managing section acquires an operational status of a standby print job when a determination that a job having been accepted by a job accepting section is a reserved low-key print setting job is made, as a result of a determination by a reserved setting determining section, and also allocates a printout for the reserved low-key print setting job to an available time slot based on the acquired operational status. As a result, the printout for the reserved low-key print setting job can be executed in an available time slot which is different from a time slot for the standby print job. Accordingly, mixing of printed sheets related to a plurality of print jobs can be prevented as much as possible, and a contribution to an improvement in convenience at the user-side can be made.

摘要翻译： 作为通过预约设定决定的判断结果，当作业接收部接受的作业是保留低音打印设定作业时，作业管理部取得待机打印作业的动作状态 部分，并且还根据获取的操作状态将保留的低调打印设置作业的打印输出分配给可用的时隙。 结果，可以在与待机打印作业的时隙不同的可用时隙中执行用于保留的低调打印设置作业的打印输出。 因此，可以尽可能地防止与多个打印作业相关的打印纸的混合，并且可以对用户侧的便利性的改善作出贡献。

公开(公告)号：US07728710B2

公开(公告)日：2010-06-01

申请号：US10541459

申请日：2004-02-05

申请人： Shinji Mizuno ,  Koji Mitsui ,  Katsutoshi Yanoshita ,  Shinichi Suzuki ,  Takashi Shinoki ,  Kazutaka Nakagome ,  Naoki Fukuda ,  Kozo Morita ,  Daisuke Makino

发明人： Shinji Mizuno ,  Koji Mitsui ,  Katsutoshi Yanoshita ,  Shinichi Suzuki ,  Takashi Shinoki ,  Kazutaka Nakagome ,  Naoki Fukuda ,  Kozo Morita ,  Daisuke Makino

IPC分类号： H01C10/32

CPC分类号： B29C45/1418 ,  B29C45/14467 ,  B29C45/14639 ,  B29L2031/3406 ,  H01C10/32 ,  H01C10/48 ,  H05K1/0393 ,  H05K1/167 ,  H05K3/0014 ,  H05K3/0058 ,  Y10T29/49082 ,  Y10T428/24917

摘要： An electronic component substrate (1-1) includes an insulating base (10) and a flexible circuit board (20) mounted on the insulating base (10). The flexible circuit board (20) is a synthetic resin film provided thereon with terminal patterns (29) and a conductor pattern (25) whose surface is slidingly contacted with a slider. The insulating base (10) is a synthetic resin molded piece. The flexible circuit board (20) is insert-molded to the insulating base (10). The electronic component substrate (1-1) is produced by preparing the flexible circuit board (20) and first and second mold members (41, 45) having a cavity (C1) with a shape that corresponds to the external shape of the electronic component substrate (1-1). Then, the flexible circuit board (20) is accommodated in the cavity (C1) between the first and second mold members (41,45), and the cavity (C1) is filled with a molten molding resin. After the molding resin has solidified, the first and second mold members (41, 45) are removed.

摘要翻译： 电子部件基板（1-1）具有安装在绝缘基体（10）上的绝缘基体（10）和柔性电路基板（20）。 柔性电路板（20）是其上设置有端子图案（29）的合成树脂膜和表面与滑块滑动接触的导体图案（25）。 绝缘基座（10）是合成树脂模制件。 柔性电路板（20）被嵌入成型到绝缘基座（10）。 电子部件基板（1-1）通过制备柔性电路板（20）和具有空腔（C1）的第一和第二模具部件（41,45）制成，其形状对应于电子部件的外部形状 基板（1-1）。 然后，柔性电路板（20）容纳在第一和第二模具构件（41,45）之间的空腔（C1）中，并且空腔（C1）填充有熔融模制树脂。 在模制树脂固化之后，移除第一和第二模具构件（41,45）。

公开(公告)号：US20050040452A1

公开(公告)日：2005-02-24

申请号：US10959634

申请日：2004-10-07

申请人： Yoshitaka Nakamura ,  Tsuyoshi Tamaru ,  Naoki Fukuda ,  Hidekazu Goto ,  Isamu Asano ,  Hideo Aoki ,  Keizo Kawakita ,  Satoru Yamada ,  Katsuhiko Tanaka ,  Hiroshi Sakuma ,  Masayoshi Hirasawa

发明人： Yoshitaka Nakamura ,  Tsuyoshi Tamaru ,  Naoki Fukuda ,  Hidekazu Goto ,  Isamu Asano ,  Hideo Aoki ,  Keizo Kawakita ,  Satoru Yamada ,  Katsuhiko Tanaka ,  Hiroshi Sakuma ,  Masayoshi Hirasawa

IPC分类号： H01L21/8242 ,  H01L23/522 ,  H01L29/76

CPC分类号： H01L27/10852 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： The semiconductor device is formed according to the following steps. A TiN film 71 and a W film 72 are deposited on a silicon oxide film 64 including the inside of a via-hole 66 by the CVD method and thereafter, the W film 72 and TiN film 71 on the silicon oxide film 64 are etched back to leave only the inside of the via-hole 66 and form a plug 73. Then, a TiN film 74, Al-alloy film 75, and Ti film 76 are deposited on the silicon oxide film 64 including the surface of the plug 73 by the sputtering method and thereafter, the Ti film 76, Al-alloy film 75, and TiN film 74 are patterned to form second-layer wirings 77 and 78.

公开(公告)号：US06492730B1

公开(公告)日：2002-12-10

申请号：US09480480

申请日：2000-01-11

申请人： Yoshitaka Nakamura ,  Tsuyoshi Tamaru ,  Naoki Fukuda ,  Hidekazu Goto ,  Isamu Asano ,  Hideo Aoki ,  Keizo Kawakita ,  Satoru Yamada ,  Katsuhiko Tanaka ,  Hiroshi Sakuma ,  Masayoshi Hirasawa

发明人： Yoshitaka Nakamura ,  Tsuyoshi Tamaru ,  Naoki Fukuda ,  Hidekazu Goto ,  Isamu Asano ,  Hideo Aoki ,  Keizo Kawakita ,  Satoru Yamada ,  Katsuhiko Tanaka ,  Hiroshi Sakuma ,  Masayoshi Hirasawa

IPC分类号： H01L2348

CPC分类号： H01L27/10852 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： The semiconductor device is formed according to the following steps. A TiN film 71 and a W film 72 are deposited on a silicon oxide film 64 including the inside of a via-hole 66 by the CVD method and thereafter, the W film 72 and TiN film 71 on the silicon oxide film 64 are etched back to leave only the inside of the via-hole 66 and form a plug 73. Then, a TiN film 74, Al-alloy film 75, and Ti film 76 are deposited on the silicon oxide film 64 including the surface of the plug 73 by the sputtering method and thereafter, the Ti film 76, Al-alloy film 75, and TiN film 74 are patterned to form second-layer wirings 77 and 78.

摘要翻译： 根据以下步骤形成半导体器件。 通过CVD法将TiN膜71和W膜72沉积在包括通孔66内部的氧化硅膜64上，然后将氧化硅膜64上的W膜72和TiN膜71回蚀 仅留下通孔66的内部并形成插头73.然后，将TiN膜74，Al合金膜75和Ti膜76沉积在包括插塞73的表面的氧化硅膜64上，通过 溅射法，然后对Ti膜76，Al合金膜75和TiN膜74进行图案化以形成第二层布线77和78。

公开(公告)号：US06399438B2

公开(公告)日：2002-06-04

申请号：US09828201

申请日：2001-04-09

申请人： Masayoshi Saito ,  Yoshitaka Nakamura ,  Hidekazu Goto ,  Keizo Kawakita ,  Satoru Yamada ,  Toshihiro Sekiguchi ,  Isamu Asano ,  Yoshitaka Tadaki ,  Takuya Fukuda ,  Masayuki Suzuki ,  Tsuyoshi Tamaru ,  Naoki Fukuda ,  Hideo Aoki ,  Masayoshi Hirasawa

发明人： Masayoshi Saito ,  Yoshitaka Nakamura ,  Hidekazu Goto ,  Keizo Kawakita ,  Satoru Yamada ,  Toshihiro Sekiguchi ,  Isamu Asano ,  Yoshitaka Tadaki ,  Takuya Fukuda ,  Masayuki Suzuki ,  Tsuyoshi Tamaru ,  Naoki Fukuda ,  Hideo Aoki ,  Masayoshi Hirasawa

IPC分类号： H01L218242

CPC分类号： H01L21/76855 ,  H01L21/28518 ,  H01L21/31604 ,  H01L21/76801 ,  H01L21/76828 ,  H01L21/76837 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/7687 ,  H01L27/10814 ,  H01L27/10885 ,  H01L27/10894 ,  H01L28/40

摘要： In a DRAM having a capacitor-over-bitline structure in which the capacitive insulating film of an information storing capacitive element C is formed of a high dielectric material such as Ta2O5 (tantalum oxide) film 46, the portions of bit lines BL and first-layer interconnect lines 23 to 26 of a peripheral circuit which are in contact with at least an underlying silicon oxide film 28 are formed of a W film, the bit lines BL and the interconnect lines 23 to 26 being arranged below the information storing capacitive element C, whereby the adhesion at the interface between the bit lines BL and the interconnect lines 23 to 26 and the silicon oxide film is improved in terms of high-temperature heat treatment to be performed when the capacitive insulating film is being formed.

摘要翻译： 在具有电容器的位线结构的DRAM中，信息存储电容元件C的电容绝缘膜由诸如Ta 2 O 5（氧化钽）膜46的高电介质材料形成，位线BL和第一 - 与W膜形成的与外部电路至少底层的氧化硅膜28接触的层间布线23〜26，位线BL和布线23〜26配置在信息存储电容元件C的下方 从而在形成电容绝缘膜时进行的高温热处理方面提高了位线BL与布线23〜26之间界面处的粘附性和氧化硅膜。

公开(公告)号：US6028360A

公开(公告)日：2000-02-22

申请号：US106074

申请日：1998-06-29

申请人： Yoshitaka Nakamura ,  Tsuyoshi Tamaru ,  Naoki Fukuda ,  Hidekazu Goto ,  Isamu Asano ,  Hideo Aoki ,  Keizo Kawakita ,  Satoru Yamada ,  Katsuhiko Tanaka ,  Hiroshi Sakuma ,  Masayoshi Hirasawa

发明人： Yoshitaka Nakamura ,  Tsuyoshi Tamaru ,  Naoki Fukuda ,  Hidekazu Goto ,  Isamu Asano ,  Hideo Aoki ,  Keizo Kawakita ,  Satoru Yamada ,  Katsuhiko Tanaka ,  Hiroshi Sakuma ,  Masayoshi Hirasawa

IPC分类号： H01L21/8242 ,  H01L23/522 ,  H01L23/48 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L23/5226 ,  H01L2924/0002

摘要： The semiconductor device is formed according to the following steps. A TiN film 71 and a W film 72 are deposited on a silicon oxide film 64 including the inside of a via-hole 66 by the CVD method and thereafter, the W film 72 and TiN film 71 on the silicon oxide film 64 are etched back to leave only the inside of the via-hole 66 and form a plug 73. Then, a TiN film 74, Al-alloy film 75, and Ti film 76 are deposited on the silicon oxide film 64 including the surface of the plug 73 by the sputtering method and thereafter, the Ti film 76, Al-alloy film 75, and TiN film 74 are patterned to form second-layer wirings 77 and 78.

摘要翻译： 根据以下步骤形成半导体器件。 通过CVD法将TiN膜71和W膜72沉积在包括通孔66内部的氧化硅膜64上，然后将氧化硅膜64上的W膜72和TiN膜71回蚀 仅留下通孔66的内部并形成插头73.然后，将TiN膜74，Al合金膜75和Ti膜76沉积在包括插塞73的表面的氧化硅膜64上，通过 溅射法，然后对Ti膜76，Al合金膜75和TiN膜74进行图案化以形成第二层布线77和78。