公开(公告)号：US20180337119A1

公开(公告)日：2018-11-22

申请号：US16048630

申请日：2018-07-30

Applicant: ATI Technologies ULC ,  Advanced Micro Devices, Inc.

Inventor： Fei Guo ,  Feng Zhu ,  Julius Din ,  Anwar Kashem ,  Sally Yeung

IPC: H01L23/498 ,  H01L23/50 ,  H01L23/14

CPC classification number: H01L23/49822 ,  H01L23/147 ,  H01L23/50 ,  H01L2224/16 ,  H01L2924/15311 ,  Y10T29/49082

Abstract: Various resistor circuits and methods of making and using the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a resistor onboard an interposer. The resistor is adapted to dampen a capacitive network. The capacitive network has at least one capacitor positioned external to the interposer.

公开(公告)号：US10074600B2

公开(公告)日：2018-09-11

申请号：US13436150

申请日：2012-03-30

Applicant: Fei Guo ,  Feng Zhu ,  Julius Din ,  Anwar Kashem ,  Sally Yeung

Inventor： Fei Guo ,  Feng Zhu ,  Julius Din ,  Anwar Kashem ,  Sally Yeung

IPC: H01C17/00 ,  H01L23/498 ,  H01L23/14 ,  H01L23/50

CPC classification number: H01L23/49822 ,  H01L23/147 ,  H01L23/50 ,  H01L2224/16 ,  H01L2924/15311 ,  Y10T29/49082

Abstract: Various resistor circuits and methods of making and using the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a resistor onboard an interposer. The resistor is adapted to dampen a capacitive network. The capacitive network has at least one capacitor positioned external to the interposer.

公开(公告)号：US20180130578A1

公开(公告)日：2018-05-10

申请号：US15650290

申请日：2017-07-14

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Jang Seok YUN ,  Kwang Hyun PARK ,  Kyung Seon BAEK

IPC: H01C17/00 ,  H01C1/14 ,  H01C17/22 ,  H01C1/01 ,  H01C1/028

CPC classification number: H01C17/006 ,  H01C1/01 ,  H01C1/028 ,  H01C1/14 ,  H01C17/22 ,  Y10T29/49082

Abstract: A chip resistor includes a board, first and second electrodes disposed on one surface of the board, and a resistor body electrically connecting the first and second electrodes to each other and including a copper-manganese-tin (Cu—Mn—Sn) alloy. In the Cu—Mn—Sn alloy, a percentage of Mn ranges from 11% to 20%, a percentage of Sn ranges from 2% to 8%, and a total percentage of Mn and Sn ranges from 13.5% to 22.5%.

公开(公告)号：US20180108459A1

公开(公告)日：2018-04-19

申请号：US15842210

申请日：2017-12-14

Applicant: ROHM CO., LTD.

Inventor： Kenichi HARADA ,  Masaki YONEDA

IPC: H01C1/14 ,  H01C17/28 ,  H01C17/00 ,  H01C17/06

CPC classification number: H01C1/14 ,  H01C17/006 ,  H01C17/06 ,  H01C17/283 ,  Y10T29/49082

Abstract: A chip resistor includes first and second electrodes spaced apart from each other, a resistor element arranged on the first and the second electrodes, a bonding layer provided between the resistor element and the two electrodes, and a plating layer electrically connected to the resistor element. The first electrode includes a flat outer side surface, and the resistor element includes a side surface facing in the direction in which the thirst and the second electrodes are spaced. The outer side surface of the first electrode is flush with the side surface of the resistor element. The plating layer covers at least a part of the outer side surface of the first electrode in a manner such that the covering portion of the plating layer extends from one vertical edge of the outer side surface to the other vertical edge.

公开(公告)号：US09891247B2

公开(公告)日：2018-02-13

申请号：US14497437

申请日：2014-09-26

Applicant: Infineon Technologies AG

Inventor： Peter Kanschat ,  Thilo Stolze

IPC: G01R1/20 ,  G01R19/00 ,  H01C17/00 ,  H01C1/144

CPC classification number: G01R1/203 ,  G01R19/0092 ,  H01C1/144 ,  H01C17/00 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/49107 ,  H01L2924/13055 ,  Y10T29/49082 ,  H01L2924/00

Abstract: A measurement resistor for current measurement is described. According to one exemplary embodiment, the measurement resistor includes a first and a second metal layer, an electrically insulating interlayer and a resistive layer. The first metal layer is arranged in a first plane. The second metal layer is arranged in a second plane that is essentially parallel to the first plane and separated from the first plane. The electrically insulating interlayer is arranged between the first and second metal layers and mechanically connects the first and second metal layers to one another. The resistive layer electrically connects the first and second metal layers to one another.

公开(公告)号：US20170287602A1

公开(公告)日：2017-10-05

申请号：US15629400

申请日：2017-06-21

Applicant: ROHM CO., LTD.

Inventor： Kenichi HARADA ,  Masaki YONEDA

IPC: H01C1/14 ,  H01C17/06 ,  H01C17/28 ,  H01C17/00

CPC classification number: H01C1/14 ,  H01C17/006 ,  H01C17/06 ,  H01C17/283 ,  Y10T29/49082

Abstract: A chip resistor includes first and second electrodes spaced apart from each other, a resistor element arranged on the first and the second electrodes, a bonding layer provided between the resistor element and the two electrodes, and a plating layer electrically connected to the resistor element. The first electrode includes a flat outer side surface, and the resistor element includes a side surface facing in the direction in which the thirst and the second electrodes are spaced. The outer side surface of the first electrode is flush with the side surface of the resistor element. The plating layer covers at least a part of the outer side surface of the first electrode in a manner such that the covering portion of the plating layer extends from one vertical edge of the outer side surface to the other vertical edge.

公开(公告)号：US20160225498A1

公开(公告)日：2016-08-04

申请号：US15012386

申请日：2016-02-01

Applicant: Vishay Dale Electronics, LLC

Inventor： Clark L. Smith ,  Thomas L. Bertsch ,  Todd L. Wyatt ,  Thomas L. Veik ,  Rodney Brune

IPC: H01C17/00 ,  H01C1/142

CPC classification number: H01C17/003 ,  H01C1/142 ,  H01C3/00 ,  H01C17/24 ,  H01C17/288 ,  Y10T29/49082 ,  Y10T29/49098

Abstract: A metal strip resistor is provided. The metal strip resistor includes a metal strip forming a resistive element and providing support for the metal strip resistor without use of a separate substrate. There are first and second opposite terminations overlaying the metal strip. There is plating on each of the first and second opposite terminations. There is also an insulating material overlaying the metal strip between the first and second opposite terminations. A method for forming a metal strip resistor wherein a metal strip provides support for the metal strip resistor without use of a separate substrate is provided. The method includes coating an insulative material to the metal strip, applying a lithographic process to form a conductive pattern overlaying the resistive material wherein the conductive pattern includes first and second opposite terminations, electroplating the conductive pattern, and adjusting resistance of the metal strip.

Abstract translation: 提供金属条电阻。 金属带状电阻器包括形成电阻元件的金属条，并且在不使用单独基板的情况下为金属带状电阻器提供支撑。 存在覆盖金属条的第一和第二相对端子。 每个第一和第二相对端子上都有电镀。 还有在第一和第二相对端子之间覆盖金属​​带的绝缘材料。 提供一种用于形成金属带状电阻器的方法，其中金属带为不使用单独基板的金属带状电阻器提供支撑。 该方法包括将绝缘材料涂覆到金属条上，施加光刻工艺以形成覆盖电阻材料的导电图案，其中导电图案包括第一和第二相对端子，电镀导电图案，以及调整金属带的电阻。

公开(公告)号：US09377430B2

公开(公告)日：2016-06-28

申请号：US14224899

申请日：2014-03-25

Applicant: Bayer HealthCare LLC

Inventor： Dijia Huang ,  Steven C. Charlton ,  Suny J. George ,  Andrew J. Edelbrock

IPC: G01N27/327 ,  C12Q1/00 ,  G01N27/416

CPC classification number: G01N27/3272 ,  C12Q1/006 ,  G01N27/3274 ,  G01N27/3275 ,  G01N27/4163 ,  Y10T29/49082 ,  Y10T29/49099

Abstract: According to one embodiment of the present invention, an electrochemical sensor (10) for detecting the concentration of analyte in a fluid test sample is disclosed. The sensor (10) includes a counter electrode having a high-resistance portion for use in detecting whether a predetermined amount of sample has been received by the test sensor.

Abstract translation: 根据本发明的一个实施例，公开了一种用于检测流体测试样品中分析物浓度的电化学传感器（10）。 传感器（10）包括具有高电阻部分的对电极，用于检测测试传感器是否已接收到预定量的样本。

公开(公告)号：US09252201B2

公开(公告)日：2016-02-02

申请号：US13780942

申请日：2013-02-28

Applicant: International Business Machines Corporation

Inventor： Roger A. Booth ,  Lawrence A. Clevenger

IPC: H05K3/30 ,  H01L49/02 ,  H01L21/311 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L28/20 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76831 ,  H01L23/5228 ,  H01L23/5329 ,  H01L23/53295 ,  H01L28/24 ,  H01L2924/0002 ,  H01L2924/12044 ,  Y10T29/49082 ,  Y10T29/4913 ,  Y10T29/49155 ,  H01L2924/00

Abstract: A stack of an interconnect-level dielectric material layer and a disposable dielectric material layer is patterned so that at least one recessed region is formed through the disposable dielectric material layer and in an upper portion of the interconnect-level dielectric material layer. A dielectric liner layer and a metallic liner layer is formed in the at least one recessed region. At least one photoresist is applied to fill the at least one recessed region and lithographically patterned to form via cavities and/or line cavities in the interconnect-level dielectric material layer. After removing the at least one photoresist, the at least one recessed region, the via cavities, and/or the line cavities are filled with at least one metallic material, which is subsequently planarized to form at least one planar resistor having a top surface that is coplanar with top surfaces of metal lines or metal vias.

Abstract translation: 互连级介电材料层和一次性介电材料层的堆叠被图案化，使得通过一次性介电材料层和互连级介电材料层的上部形成至少一个凹陷区域。 在所述至少一个凹部区域中形成介电衬垫层和金属衬垫层。 施加至少一个光致抗蚀剂以填充至少一个凹陷区域并且被光刻图案化以在互连级介电材料层中形成通孔和/或线腔。 在去除至少一个光致抗蚀剂之后，至少一个凹陷区域，通孔腔体和/或线腔体填充有至少一种金属材料，其随后被平坦化以形成至少一个具有顶表面的平面电阻器， 与金属线或金属通孔的顶面共面。

公开(公告)号：US20150270036A1

公开(公告)日：2015-09-24

申请号：US14662625

申请日：2015-03-19

Applicant: NGK Insulators, Ltd.

Inventor： Satoshi YAMAZAKI ,  Toru HAYASE ,  Kenji MORIMOTO ,  Shinji KAWASAKI ,  Yukihisa TAKEUCHI

IPC: H01C7/10 ,  H01C17/00

CPC classification number: H01C7/112 ,  C04B35/453 ,  C04B35/62695 ,  C04B37/005 ,  C04B37/006 ,  C04B2235/3217 ,  C04B2235/322 ,  C04B2235/3267 ,  C04B2235/3277 ,  C04B2235/3284 ,  C04B2235/3286 ,  C04B2235/3294 ,  C04B2235/3298 ,  C04B2235/443 ,  C04B2235/5436 ,  C04B2235/5454 ,  C04B2235/658 ,  C04B2235/6586 ,  C04B2235/661 ,  C04B2235/96 ,  C04B2237/06 ,  C04B2237/125 ,  C04B2237/126 ,  C04B2237/34 ,  C04B2237/708 ,  C04B2237/72 ,  H01C7/10 ,  H01C7/1006 ,  H01C7/102 ,  H01C7/12 ,  H01C7/18 ,  H01C17/00 ,  Y10T29/49082

Abstract: A voltage nonlinear resistive element 10 includes a resistor 14 containing a joined body 12 in which a zinc oxide ceramic layer 12a composed mainly of zinc oxide and having a volume resistivity of 1.0×10−1 Ωcm or less is joined to a bismuth oxide layer 12b composed mainly of bismuth oxide, and a pair of electrodes 16 and 18 disposed on the resistor 14 such that an electrically conductive path passes through a junction between the zinc oxide ceramic layer 12a and the bismuth oxide layer 12b. In this element 10, the zinc oxide ceramic layer 12a of the joined body 12 has a lower volume resistivity than before. This can result in a lower clamping voltage in a high-current region than before.

Abstract translation: 电压非线性电阻元件10包括电阻器14，其包含接合体12，其中主要由氧化锌组成的体积电阻率为1.0×10-1＆OHgr·cm以下的氧化锌陶瓷层12a与氧化铋 主要由氧化铋构成的层12b和设置在电阻器14上的一对电极16和18，使得导电路径通过氧化锌陶瓷层12a和氧化铋层12b之间的接合点。 在该元件10中，接合体12的氧化锌陶瓷层12a的体积电阻率比以前低。 这可能导致在高电流区域中比以前更低的钳位电压。