公开(公告)号：US20240138167A1

公开(公告)日：2024-04-25

申请号：US18278199

申请日：2022-02-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hiromichi GODO ,  Yoshiyuki KUROKAWA ,  Kouhei TOYOTAKA ,  Kazuki TSUDA ,  Satoru OHSHITA ,  Hidefumi RIKIMARU

IPC: H10K39/34 ,  G06F3/01 ,  G09G3/3208 ,  H10K59/65

CPC classification number: H10K39/34 ,  G06F3/013 ,  G09G3/3208 ,  H10K59/65 ,  G09G2330/021 ,  G09G2354/00 ,  G09G2360/14

Abstract: An electronic device having an eye tracking function is provided. The electronic device includes a display device and an optical system. The display device includes a first light-emitting element, a second light-emitting element, a sensor portion, and a driver circuit portion. The sensor portion includes a light-receiving element. The first light-emitting element has a function of emitting infrared light or visible light. The second light-emitting element has a function of emitting light of a color different from that of light emitted from the first light-emitting element. When the first light-emitting element emits infrared light, the light-receiving element has a function of detecting the infrared light that is emitted from the first light-emitting element and reflected by an eyeball of a user. When the first light-emitting element emits visible light, the light-receiving element has a function of detecting the visible light that is emitted from the first light-emitting element and reflected by the eyeball of the user. The first light-emitting element and the second light-emitting element are placed in one layer. The layer where the first light-emitting element and the second light-emitting element are positioned overlaps with the sensor portion.

公开(公告)号：US20240256037A1

公开(公告)日：2024-08-01

申请号：US18594319

申请日：2024-03-04

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yoshiyuki KUROKAWA ,  Hiromichi GODO ,  Kouhei TOYOTAKA ,  Kazuki TSUDA ,  Satoru OHSHITA ,  Hidefumi RIKIMARU

IPC: G06F3/01 ,  G02B27/01 ,  G09G3/00 ,  G09G3/3225 ,  H01L27/12 ,  H01L29/786 ,  H10K59/121

CPC classification number: G06F3/013 ,  G02B27/0172 ,  G09G3/002 ,  G09G3/3225 ,  H10K59/1213 ,  G02B2027/0178 ,  G09G2354/00 ,  G09G2360/14 ,  H01L27/1225 ,  H01L27/1251 ,  H01L27/1255 ,  H01L29/78648 ,  H01L29/78651 ,  H01L29/7869

Abstract: To provide a novel electronic device. The electronic device includes a housing and a display device. The display device includes a first layer, a second layer, and a third layer. The first layer, the second layer, and the third layer are provided in different layers. The first layer includes a driver circuit and an arithmetic circuit. The second layer includes pixel circuits and a cell array. The third layer includes light-receiving devices and light-emitting devices. The pixel circuits each have a function of controlling light emission of the light-emitting device. The driver circuit has a function of controlling the pixel circuits. The arithmetic circuit has a function of performing arithmetic processing on the basis of first data corresponding to currents output from the light-receiving devices and second data corresponding to a potential held in the cell array.

公开(公告)号：US20230386544A1

公开(公告)日：2023-11-30

申请号：US18245098

申请日：2021-09-07

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Hiromichi GODO ,  Yoshiyuki KUROKAWA ,  Kazuki TSUDA ,  Satoru OHSHITA

IPC: G11C11/22 ,  H10B53/30 ,  H10B51/30 ,  H01L21/28 ,  H01L29/78

CPC classification number: G11C11/223 ,  G11C11/221 ,  G11C11/2297 ,  H10B53/30 ,  H10B51/30 ,  H01L29/40111 ,  H01L29/78391

Abstract: A semiconductor device with low power consumption is provided. The semiconductor device includes a first transistor, a second transistor, and a capacitor. The first transistor includes a first gate and a first back gate, and the second transistor includes a second gate and a second back gate. A gate insulating layer for the first back gate has ferroelectricity. The first transistor has a function of, when being in an off state, retaining a first potential corresponding to first data. The second transistor has a function of making an output current flow between a source and a drain of the second transistor.

公开(公告)号：US20230284429A1

公开(公告)日：2023-09-07

申请号：US18016745

申请日：2021-07-19

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hiromichi GODO ,  Kazuki TSUDA ,  Yoshiyuki KUROKAWA ,  Satoru OHSHITA ,  Takuro KANEMURA ,  Hidefumi RIKIMARU

IPC: H10B12/00 ,  G11C11/405 ,  G11C11/54

CPC classification number: H10B12/00 ,  G11C11/405 ,  G11C11/54

Abstract: Provided is a semiconductor device having a novel structure. A first transistor, a second transistor, a third transistor, and a capacitor are included. The first transistor has a function of retaining a first potential corresponding to first data supplied to a gate of the third transistor through the first transistor when being in an off state. The capacitor has a function of changing the first potential retained in the gate of the third transistor into a second potential in accordance with a change in potential corresponding to second data supplied to one electrode of the capacitor. The second transistor has a function of setting a potential of one of a source and a drain of the third transistor to a potential corresponding to a potential of a gate of the second transistor. The third transistor has a function of supplying output current corresponding to a potential of the gate of the third transistor to the other of the source and the drain of the third transistor. The output current is current flowing when the third transistor operates in a subthreshold region.

公开(公告)号：US20230273637A1

公开(公告)日：2023-08-31

申请号：US18024198

申请日：2021-08-25

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshiyuki KUROKAWA ,  Kazuki TSUDA ,  Hiromichi GODO ,  Satoru OHSHITA ,  Takuro KANEMURA ,  Hidefumi RIKIMARU ,  Takayuki IKEDA ,  Yuto YAKUBO ,  Shunpei YAMAZAKI

IPC: G05F3/24 ,  H01M10/42

CPC classification number: G05F3/24 ,  H01M10/425

Abstract: A control circuit of a secondary battery with a novel structure is provided. The control circuit of a secondary battery includes a first transistor, a first voltage generation circuit generating a first voltage, and a second voltage generation circuit generating a second voltage. The first voltage generation circuit includes a second transistor and a first capacitor. The second voltage generation circuit includes a third transistor and a second capacitor. The difference between the first voltage and the second voltage is set in accordance with the threshold voltage of the first transistor. When the first transistor includes a back gate, a voltage retention circuit having a function of retaining the voltage of the back gate is included. The voltage retention circuit includes a fourth transistor and a third capacitor. The third capacitor includes a ferroelectric layer between a pair of electrodes. The third capacitor retains a voltage applied to the back gate by being applied with a voltage for polarization inversion in the ferroelectric layer.

公开(公告)号：US20240237435A1

公开(公告)日：2024-07-11

申请号：US18288495

申请日：2022-04-20

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kazuki TSUDA ,  Hidefumi RIKIMARU ,  Satoru OHSHITA ,  Hiromichi GODO ,  Yoshiyuki KUROKAWA

IPC: H10K59/131

CPC classification number: H10K59/131

Abstract: A semiconductor device with reduced circuit area is provided. The semiconductor device includes first and second cell arrays and a first converter circuit. The first cell array includes a first cell and a second cell in the same row, and the second cell array includes third and fourth cells in the same row. The first cell is electrically connected to first and second wirings, the second cell is electrically connected to the first and third wirings, the third cell is electrically connected to fourth and sixth wirings, and the fourth cell is electrically connected to fifth and seventh wirings. The sixth wiring is electrically connected to the seventh wiring. The first to fourth cells each have a function of outputting current corresponding to a product of retained data and input data. Specifically, the first cell, the second cell, the third cell, and the fourth cell output current to the second wiring, the third wiring, the sixth wiring, and the seventh wiring, respectively. The first converter circuit has a function of making data corresponding to a total amount of current flowing through the second and third wirings flow to the fourth and fifth wirings, respectively.

公开(公告)号：US20240134605A1

公开(公告)日：2024-04-25

申请号：US18278451

申请日：2022-02-24

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yoshiyuki KUROKAWA ,  Hiromichi GODO ,  Kazuki TSUDA ,  Satoru OHSHITA ,  Hidefumi RIKIMARU

IPC: G06F7/523 ,  G06F7/50 ,  G09G3/3208 ,  G11C11/405 ,  H10B12/00 ,  H10K59/121

CPC classification number: G06F7/523 ,  G06F7/50 ,  G09G3/3208 ,  G11C11/405 ,  H10B12/00 ,  H10K59/1213 ,  H10K59/1216

Abstract: A semiconductor device with a novel structure is provided. The semiconductor device includes a cell array performing a product-sum operation of a first layer and a product-sum operation of a second layer in an artificial neural network, a first circuit from which first data is input to the cell array, and a second circuit to which second data is output from the cell array. The cell array includes a plurality of cells. The cell array includes a first region and a second region. In a first period, the first region is supplied with the t-th (t is a natural number greater than or equal to 2) first data from the first circuit and outputs the t-th second data according to the product-sum operation of the first layer to the second circuit. In the first period, the second region is supplied with the (t+1)-th first data from the first circuit and outputs the (t+1)-th second data according to the product-sum operation of the second layer to the first circuit.

公开(公告)号：US20230369329A1

公开(公告)日：2023-11-16

申请号：US18142740

申请日：2023-05-03

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshiyuki KUROKAWA ,  Satoru OHSHITA ,  Hidefumi RIKIMARU

IPC: H01L27/092 ,  H03M1/72

CPC classification number: H01L27/092 ,  H03M1/72

Abstract: A semiconductor device with low power consumption is provided. The semiconductor device includes a first layer and a second layer. The first layer includes a first cell and a first to a third circuit, and the second layer includes a second cell and a fourth and a fifth circuit. The first, second, and fourth circuits each have a function of converting digital data into analog current. The first cell calculates a product of a value from the first current and a value from the second circuit and inputs a calculation result into a third circuit as current. The third circuit generates analog current from the input current. The second cell calculates a product of a value from the third circuit and a value from the fourth circuit and inputs a calculation result into the fifth circuit as current. The fifth circuit generates analog current from the input current.

公开(公告)号：US20220399355A1

公开(公告)日：2022-12-15

申请号：US17776342

申请日：2020-11-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kazuki TSUDA ,  Hiromichi GODO ,  Satoru OHSHITA ,  Hitoshi KUNITAKE

IPC: H01L27/11524 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: A novel semiconductor device is provided. A structure body extending in a first direction, a first conductor extending in a second direction, and a second conductor extending in the second direction are provided. In a first intersection portion where the structure body and the first conductor intersect with each other, a first insulator, a first semiconductor, a second insulator, a second semiconductor, a third insulator, a fourth insulator, and a fifth insulator are provided concentrically around a third conductor. In a second intersection portion where the structure body and the second conductor intersect with each other, the first insulator, the first semiconductor, the second insulator, a fourth conductor, the second semiconductor, and the third insulator are provided concentrically around the third conductor.

公开(公告)号：US20220352384A1

公开(公告)日：2022-11-03

申请号：US17760836

申请日：2020-09-11

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Masashi OOTA ,  Yoshinori ANDO ,  Shuhei NAGATSUKA ,  Tatsuki KOSHIDA ,  Satoru OHSHITA ,  Ryota HODO ,  Kazuki TSUDA ,  Akio SUZUKI

IPC: H01L29/786 ,  H01L27/108 ,  H01L29/66

Abstract: A semiconductor device that is suitable for high integration is provided. A first layer provided with a first transistor including an oxide semiconductor, over a substrate; a second layer over the first layer; a third layer provided with a second transistor including an oxide semiconductor, over the second layer; a fourth layer between the first layer and the second layer; and a fifth layer between the second layer and the third layer are included. The total internal stress of the first layer and the total internal stress of the third layer act in a first direction, the total internal stress of the second layer acts in the direction opposite to the first direction, and the fourth layer and the fifth layer each include a film having a barrier property.