-
公开(公告)号：US20250054523A1
公开(公告)日：2025-02-13
申请号：US18932891
申请日：2024-10-31
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Takeshi AOKI , Yoshiyuki KUROKAWA , Munehiro KOZUMA , Takuro KANEMURA , Tatsunori INOUE
Abstract: A semiconductor device with a small circuit area and low power consumption is provided. The semiconductor device includes first to fourth cells, a current mirror circuit, and first to fourth wirings, and the first to fourth cells each include a first transistor, a second transistor, and a capacitor. In each of the first to fourth cells, a first terminal of the first transistor is electrically connected to a first terminal of the capacitor and a gate of the second transistor. The first wiring is electrically connected to first terminals of the second transistors in the first cell and the second cell, the second wiring is electrically connected to first terminals of the second transistors in the third cell and the fourth cell, the third wiring is electrically connected to second terminals of the capacitors in the first cell and the third cell, and the fourth wiring is electrically connected to second terminals of the capacitors in the second cell and the fourth cell. The current mirror circuit is electrically connected to the first wiring and the second wiring.
-
公开(公告)号：US20220276834A1
公开(公告)日：2022-09-01
申请号：US17625392
申请日：2020-06-29
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor： Takeshi AOKI , Yoshiyuki KUROKAWA , Munehiro KOZUMA , Takuro KANEMURA
IPC: G06F7/544 , H01L27/108 , H01L27/12 , H01L29/786 , G11C11/405 , G11C11/408 , G11C11/4094 , G11C11/4096
Abstract: A semiconductor device which can efficiently perform reading of a weight coefficient and a product-sum operation is provided. The semiconductor device includes a product-sum operation circuit and a memory device. The product-sum operation circuit is formed using transistors formed on a semiconductor substrate, and a memory cell of the memory device is formed using an OS transistor provided to be stacked above the semiconductor substrate. The semiconductor device includes a plurality of product-sum operation units where the product-sum operation circuit and the memory cell of the memory device are electrically connected to each other. In each of the product-sum operation units, a weight coefficient stored in the memory cell can be read and a product-sum operation can be performed.
-
公开(公告)号：US20230284429A1
公开(公告)日：2023-09-07
申请号：US18016745
申请日：2021-07-19
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Hiromichi GODO , Kazuki TSUDA , Yoshiyuki KUROKAWA , Satoru OHSHITA , Takuro KANEMURA , Hidefumi RIKIMARU
IPC: H10B12/00 , G11C11/405 , G11C11/54
CPC classification number: H10B12/00 , G11C11/405 , G11C11/54
Abstract: Provided is a semiconductor device having a novel structure. A first transistor, a second transistor, a third transistor, and a capacitor are included. The first transistor has a function of retaining a first potential corresponding to first data supplied to a gate of the third transistor through the first transistor when being in an off state. The capacitor has a function of changing the first potential retained in the gate of the third transistor into a second potential in accordance with a change in potential corresponding to second data supplied to one electrode of the capacitor. The second transistor has a function of setting a potential of one of a source and a drain of the third transistor to a potential corresponding to a potential of a gate of the second transistor. The third transistor has a function of supplying output current corresponding to a potential of the gate of the third transistor to the other of the source and the drain of the third transistor. The output current is current flowing when the third transistor operates in a subthreshold region.
-
公开(公告)号：US20230273637A1
公开(公告)日：2023-08-31
申请号：US18024198
申请日：2021-08-25
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Yoshiyuki KUROKAWA , Kazuki TSUDA , Hiromichi GODO , Satoru OHSHITA , Takuro KANEMURA , Hidefumi RIKIMARU , Takayuki IKEDA , Yuto YAKUBO , Shunpei YAMAZAKI
CPC classification number: G05F3/24 , H01M10/425
Abstract: A control circuit of a secondary battery with a novel structure is provided. The control circuit of a secondary battery includes a first transistor, a first voltage generation circuit generating a first voltage, and a second voltage generation circuit generating a second voltage. The first voltage generation circuit includes a second transistor and a first capacitor. The second voltage generation circuit includes a third transistor and a second capacitor. The difference between the first voltage and the second voltage is set in accordance with the threshold voltage of the first transistor. When the first transistor includes a back gate, a voltage retention circuit having a function of retaining the voltage of the back gate is included. The voltage retention circuit includes a fourth transistor and a third capacitor. The third capacitor includes a ferroelectric layer between a pair of electrodes. The third capacitor retains a voltage applied to the back gate by being applied with a voltage for polarization inversion in the ferroelectric layer.
-
公开(公告)号：US20230049977A1
公开(公告)日：2023-02-16
申请号：US17785510
申请日：2020-12-14
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Yoshiyuki KUROKAWA , Munehiro KOZUMA , Takeshi AOKI , Takuro KANEMURA
IPC: G06N3/063 , G11C11/405 , H01L27/108 , H01L27/12 , H01L29/786 , G06F7/544
Abstract: A semiconductor device that has low power consumption and is capable of performing arithmetic operation is provided. The semiconductor device includes first to third circuits and first and second cells. The first cell includes a first transistor, and the second cell includes a second transistor. The first and second transistors operate in a subthreshold region. The first cell is electrically connected to the first circuit, the first cell is electrically connected to the second and third circuits, and the second cell is electrically connected to the second and third circuits. The first cell sets current flowing from the first circuit to the first transistor to a first current, and the second cell sets current flowing from the second circuit to the second transistor to a second current. At this time, a potential corresponding to the second current is input to the first cell. Then, a sensor included in the third circuit supplies a third current to change a potential of the second wiring, whereby the first cell outputs a fourth current corresponding to the first current and the amount of change in the potential.
-
Patent Agency Ranking
公开(公告)号：US20230326491A1
公开(公告)日：2023-10-12
申请号：US17922659
申请日：2021-05-06
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Takeshi AOKI , Yoshiyuki KUROKAWA , Munehiro KOZUMA , Takuro KANEMURA , Tatsunori INOUE
CPC classification number: G11C5/10 , G11C11/221 , H01L29/6684 , H01L29/78391 , H10B53/30
Abstract: A semiconductor device with a small circuit area and low power consumption is provided. The semiconductor device includes first to fourth cells, a current mirror circuit, and first to fourth wirings, and the first to fourth cells each include a first transistor, a second transistor, and a capacitor. In each of the first to fourth cells, a first terminal of the first transistor is electrically connected to a first terminal of the capacitor and a gate of the second transistor. The first wiring is electrically connected to first terminals of the second transistors in the first cell and the second cell, the second wiring is electrically connected to first terminals of the second transistors in the third cell and the fourth cell, the third wiring is electrically connected to second terminals of the capacitors in the first cell and the third cell, and the fourth wiring is electrically connected to second terminals of the capacitors in the second cell and the fourth cell. The current mirror circuit is electrically connected to the first wiring and the second wiring.
-
公开(公告)号：US20230082313A1
公开(公告)日：2023-03-16
申请号：US17799977
申请日：2021-02-12
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor： Takeshi AOKI , Yoshiyuki KUROKAWA , Munehiro KOZUMA , Takuro KANEMURA
IPC: G06F7/544 , G11C11/405 , H01L27/108 , H01L27/12 , H01L29/786 , G06N3/04
Abstract: A semiconductor device with reduced power consumption that can perform a product-sum operation is provided. The semiconductor device includes first and second circuits, and the second circuit includes first and second switches, a current/voltage converter circuit, and a first transistor. The first circuit is electrically connected to a first terminal of the second circuit; a first terminal of the first switch is electrically connected to the first terminal of the second circuit; a second terminal of the first switch is electrically connected to an input terminal of the current/voltage converter circuit; an output terminal of the current/voltage converter circuit is electrically connected to a first terminal of the first transistor; a second terminal of the first transistor is electrically connected to a first terminal of the second switch; and a second terminal of the second switch is electrically connected to a second terminal of the second circuit. The first circuit has a function of retaining a plurality of pieces of first data and a function of making a current in an amount responsive to the sum of products of the plurality of pieces of first data and a plurality of pieces of second data flow to the first terminal of the second circuit when the plurality of pieces of second data are input to the first circuit.
-
公开(公告)号：US20230043910A1
公开(公告)日：2023-02-09
申请号：US17793104
申请日：2021-01-08
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Yoshiyuki KUROKAWA , Munehiro KOZUMA , Takeshi AOKI , Takuro KANEMURA
Abstract: A semiconductor device that has low power consumption and is capable of performing a product-sum operation is provided. The semiconductor device includes first and second cells, a first circuit, and first to third wirings. Each of the first and second cells includes a capacitor, and a first terminal of each of the capacitors is electrically connected to the third wiring. Each of the first and second cells has a function of feeding a current based on a potential held at a second terminal of the capacitor, to a corresponding one of the first and second wirings. The first circuit is electrically connected to the first and second wirings and stores currents I1 and I2 flowing through the first and second wirings. When the potential of the third wiring changes and accordingly the amount of current of the first wiring changes from I1 to I3 and the amount of current of the second wiring changes from I2 to I4, the first circuit generates a current with an amount I1-I2-I3+I4. Note that the potential of the third wiring is changed by firstly inputting a reference potential to the third wiring and then inputting a potential based on internal data or a potential based on information obtained by a sensor.
-
公开(公告)号：US20230353163A1
公开(公告)日：2023-11-02
申请号：US18018965
申请日：2021-07-26
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Takuro KANEMURA , Yoshiyuki KUROKAWA , Hiromichi GODO , Kazuki TSUDA , Satoru OHSHITA , Hidefumi RIKIMARU
IPC: G09G3/3233 , H03M1/46
CPC classification number: H03M1/46 , G09G3/3233 , H03K5/2472
Abstract: A novel semiconductor device is provided. An analog signal is converted into a digital signal using a comparison portion comparing two current values, a control portion, and a current output digital-analog conversion portion. The control portion has a function of generating a sign bit showing a magnitude relation between the two current values, a function of converting a difference between the two current values into a digital signal by successive approximation, and a function of outputting the sign bit and the digital signal.
-
公开(公告)号：US20230132059A1
公开(公告)日：2023-04-27
申请号：US17915673
申请日：2021-04-05
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Yoshiyuki KUROKAWA , Munehiro KOZUMA , Takeshi AOKI , Takuro KANEMURA
Abstract: A semiconductor device capable of performing product-sum operation with high layout flexibility is provided. In the semiconductor device, a first layer, a second layer, and a third layer are formed in this order. The first layer includes a first cell, a first circuit, a first wiring, and a second wiring adjacent to the first wiring. The second layer includes a third wiring and a fourth wiring adjacent to the third wiring. The third layer includes an electrode and a sensor. The first circuit includes a switch. The sensor is electrically connected to the third wiring through the electrode and a first plug, a first terminal of the switch is electrically connected to the third wiring through a second plug, and a second terminal of the switch is electrically connected to the first cell through the first wiring. The electrode includes a region overlapping with the sensor and a region overlapping with the first plug. Note that the first to fourth wirings are parallel to each other, and the distance between the third wiring and the fourth wiring is greater than or equal to 0.9 times and less than or equal to 1.1 times the distance between the first wiring and the second wiring.
-
-
-
-
-
-
-
-
-
Search Results
12
records
(took 0.022 seconds)
