公开(公告)号：US5904570A

公开(公告)日：1999-05-18

申请号：US650357

申请日：1996-05-20

申请人： Sen-Fu Chen ,  Bao-Ru Yang ,  Wen-Cheng Chang ,  Heng-Hsin Liu

发明人： Sen-Fu Chen ,  Bao-Ru Yang ,  Wen-Cheng Chang ,  Heng-Hsin Liu

IPC分类号： H01L21/02 ,  H01L21/3213 ,  H01L21/306

CPC分类号： H01L21/02071

摘要： The polymeric residues which remain after the plasma-enhanced subtractive etching of polycrystalline layers in reactive halogen-containing gases are removed by a combination ashing in oxygen gas and subsequent removal with an organic solvent.

摘要翻译： 在反应性含卤素气体中的多晶层的等离子体增强的减去蚀刻之后残留的聚合物残余物通过氧气中的灰分组合并随后用有机溶剂去除而被除去。

公开(公告)号：US5763316A

公开(公告)日：1998-06-09

申请号：US800977

申请日：1997-02-19

申请人： Sen-Fu Chen ,  Bao-Ru Yang ,  Wen-Cheng Chang

发明人： Sen-Fu Chen ,  Bao-Ru Yang ,  Wen-Cheng Chang

IPC分类号： H01L21/32 ,  H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76216 ,  H01L21/32

摘要： A process for creating field oxide isolation for the micron and sub-micron devices in the high density integrated circuits has been developed. The junction leakage problem resulted from the trenches in the substrate formed after the removal of the silicon nitride mask, is avoided. The encroachment of the "bird's beak" into the small active device region is also minimized by this invention. These goals are accomplished by the addition of a polysilicon or amorphous silicon refill layer in the trenches after the removal of the silicon nitride oxidation mask in the isolation region, prior to field oxide oxidation process.

摘要翻译： 已经开发了用于在高密度集成电路中为微米和亚微米器件创建场氧化物隔离的工艺。 避免了在去除氮化硅掩模之后形成的衬底中的沟槽产生的结漏电问题。 本发明也将“鸟嘴”侵入小活动装置区域也被最小化。 这些目标通过在场氧化物氧化过程之前在隔离区域中去除氮化硅氧化掩模之后，在沟槽中添加多晶硅或非晶硅填充层来实现。

公开(公告)号：US5719087A

公开(公告)日：1998-02-17

申请号：US612043

申请日：1996-03-07

申请人： Sen Fu Chen ,  Jie Shing Wu ,  Po-Tau Chu ,  Wen-Cheng Chang

发明人： Sen Fu Chen ,  Jie Shing Wu ,  Po-Tau Chu ,  Wen-Cheng Chang

IPC分类号： H01L21/473 ,  H01L21/60 ,  H01L21/44

CPC分类号： H01L21/473 ,  H01L24/11 ,  H01L2224/13099 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01082 ,  H01L2924/14

摘要： A protective cap of dielectric material is deposited by plasma-enhanced chemical vapor deposition on the surface of electrical bonding pads of semiconductor integrated circuits prior to deposition of the final passivation layer. The protective cap serves to isolate the pad surface from electrochemical or other interaction with the etching solution used to open contact holes through the passivation layer. This prevents the formation of surface damage and residues on the pad which lead to yield and reliability problem with integrated circuits.

摘要翻译： 在沉积最终钝化层之前，通过等离子体增强化学气相沉积在半导体集成电路的电接合焊盘的表面上沉积电介质材料的保护帽。 保护盖用于将焊盘表面与用于打开通过钝化层的接触孔的蚀刻溶液的电化学或其它相互作用隔离。 这可以防止表面损伤和焊盘上的残留物的形成，从而导致集成电路的产量和可靠性问题。

公开(公告)号：US20200305635A1

公开(公告)日：2020-10-01

申请号：US16728818

申请日：2019-12-27

申请人： Wen-Cheng Chang

发明人： Wen-Cheng Chang

IPC分类号： A47J31/46 ,  A47J31/20 ,  A47J31/60 ,  A47J31/52

摘要： An intelligent extraction beverage cooler comprises a casing and a heating cylinder installed in the casing, a hot liquid container, a cold liquid container, a pot lid, a pot lid lifting mechanism, and a cooling system with multiple connecting pipes. The pot lid lifting mechanism drives the pot lid to lower into the hot liquid container along with an ingredient bag. The heating cylinder heats up the liquid and transports it to the hot liquid container. The ingredient bag is extracted to produce a hot beverage which is made into an iced liquid beverage by the cooling system without affecting taste thereof. This avoids bitterness or rancid taste of the hot liquid beverage. Additionally, the pot lid lifting mechanism drives the pot lid to open for convenience of putting in the ingredient bag.

公开(公告)号：US07100898B1

公开(公告)日：2006-09-05

申请号：US11247461

申请日：2005-10-11

申请人： Wen-Cheng Chang

发明人： Wen-Cheng Chang

IPC分类号： B66F3/24

CPC分类号： B66F3/12 ,  B66F3/25 ,  B66F3/44

摘要： A lifting jack includes a lifting mechanism pivoted to a base and a support bracket member so as to lift or lower the support bracket member relative to the base, a driving shaft journalled on a right link pin to be rotated so as to move a left link pin relative to the right link pin, a reflecting member hinged to the base so as to enable the reflecting member to be displaced from a folded position to an unfolded position and to be disposed to reflect images of an object lifted by the support bracket member. Preferably, a lighting device is disposed to illuminate a desired area of the object. Two limit switches are disposed to prevent excess movement of the bracket support member.

摘要翻译： 提升千斤顶包括枢转到基座的提升机构和支撑托架构件，以便相对于基座提升或降低支撑托架构件，驱动轴轴颈安装在右连杆销上以便旋转以便使左连杆 销相对于右连杆销，反射构件铰接到基座，以使得反射构件能够从折叠位置移动到展开位置，并且被布置成反射由支撑支架构件提升的物体的图像。 优选地，照明装置设置成照亮物体的期望区域。 设置两个限位开关以防止托架支撑构件的过度运动。

公开(公告)号：US6054359A

公开(公告)日：2000-04-25

申请号：US332426

申请日：1999-06-14

申请人： Yu-Ming Tsui ,  Wen-Cheng Chang ,  Shung-Jen Yu ,  Sheng-Yih Ting

发明人： Yu-Ming Tsui ,  Wen-Cheng Chang ,  Shung-Jen Yu ,  Sheng-Yih Ting

IPC分类号： H01L21/02 ,  H01L27/06 ,  H01L21/8244

CPC分类号： H01L28/20 ,  H01L27/0629

摘要： A high-sheet-resistance polysilicon resistor for integrated circuits is achieved by using a two-layer polysilicon process. After forming FET gate electrodes and capacitor bottom electrodes from a polycide layer, a thin interpolysilicon oxide (IPO) layer is deposited to form the capacitor interelectrode dielectric. A doped polysilicon layer and an undoped polysilicon layer are deposited and patterned to form the resistor. The doped polysilicon layer is in-situ doped to minimize the temperature and voltage coefficients of resistivity. Since the undoped polysilicon layer has a very high resistance (infinite), the resistance is predominantly determined by the doped polysilicon layer. The doped polysilicon layer can be reduced in thickness (less than 1000 Angstroms) to further increase the sheet resistance for mixed-mode circuits, while the undoped polysilicon layer allows contact openings to be etched in an insulating layer over the resistor without overetching the thin doped polysilicon layer and damaging the underlying IPO layer.

摘要翻译： 用于集成电路的高电阻多晶硅电阻器通过使用两层多晶硅工艺实现。 在从多晶硅层形成FET栅电极和电容器底电极之后，沉积薄的多晶硅氧化物（IPO）层以形成电容器电极间电介质。 沉积掺杂多晶硅层和未掺杂多晶硅层并构图以形成电阻器。 掺杂多晶硅层被原位掺杂以最小化电阻率的温度和电压系数。 由于未掺杂的多晶硅层具有非常高的电阻（无限大），所以电阻主要由掺杂多晶硅层决定。 掺杂多晶硅层可以减小厚度（小于1000埃），以进一步提高混合模式电路的薄层电阻，而未掺杂的多晶硅层允许在电阻器上的绝缘层中蚀刻接触开口，而不会过滤掉掺杂 多晶硅层，并损坏底层的IPO层。

公开(公告)号：US09350616B1

公开(公告)日：2016-05-24

申请号：US12777688

申请日：2010-05-11

申请人： Ju-Chun Lou ,  Wen-Cheng Chang ,  Yen-Chiu Ku ,  Ren-Chien Chou ,  Jui-Hao Lin

发明人： Ju-Chun Lou ,  Wen-Cheng Chang ,  Yen-Chiu Ku ,  Ren-Chien Chou ,  Jui-Hao Lin

IPC分类号： G06F15/173 ,  H04L12/24 ,  H04L12/26 ,  G06F11/34 ,  H04W28/02 ,  H04W24/08 ,  H04L12/911 ,  G06F9/50 ,  H04W40/18 ,  H04W24/02 ,  H04L12/801 ,  H04L12/919

CPC分类号： H04L41/0896 ,  G06F9/5072 ,  G06F11/3409 ,  G06F11/3442 ,  H04L41/147 ,  H04L43/0805 ,  H04L43/0852 ,  H04L43/16 ,  H04L47/12 ,  H04L47/29 ,  H04L47/765 ,  H04L47/822 ,  H04L47/823 ,  H04W24/02 ,  H04W24/08 ,  H04W28/0289 ,  H04W40/18

摘要： A software module on a client computer sends a query to a remote computer server operating a cloud service and receives a response, in order to determine latency. The latency is used with the total size of the packets sent and the packet size to determine the bandwidth available over the network connection at that time. Bandwidth available is calculated periodically and stored in a database of the client computer. Comparing a calculated bandwidth with predefined threshold values indicates whether the network status is good for initiating a cloud service with the computer server or poor. Any number of bandwidth available values are used to determine a slope and the slope is used to predict a bandwidth available value at a future time. A bandwidth available moving average is calculated by summing the bandwidth values for the previous days and dividing by the number of days; the moving average is calculated periodically.

摘要翻译： 客户端计算机上的软件模块向运行云服务的远程计算机服务器发送查询，并接收响应，以确定延迟。 延迟与发送的分组的总大小和分组大小一起使用，以确定当时通过网络连接可用的带宽。 可用的带宽定期计算并存储在客户端计算机的数据库中。 将计算的带宽与预定义的阈值进行比较表示网络状态是否适合发起计算机服务器或差的云服务。 使用任何数量的带宽可用值来确定斜率，并且斜率用于预测未来时间的带宽可用值。 带宽可用移动平均值通过对前几天的带宽值求和除以天数来计算; 周期性地计算移动平均值。

公开(公告)号：US20110061213A1

公开(公告)日：2011-03-17

申请号：US12558710

申请日：2009-09-14

申请人： Wen-Cheng Chang

发明人： Wen-Cheng Chang

IPC分类号： A44B11/02

CPC分类号： B60P7/083 ,  Y10T24/2175

摘要： A hand puller with the structure of double stopping plates is disclosed. An axle part goes through a fixing part and a pulling part. Both ends of the axle part have a ratchet, respectively. The fixing part has two stopping plates, fixed to the two opposite sides of the axle part. The pulling part has a driving claw. The driving claw and the stopping plates of the fixing part engage with the ratchet.

摘要翻译： 公开了具有双止动板结构的手拉机。 轴部穿过固定部分和牵引部分。 轴部的两端分别具有棘轮。 固定部分具有两个止动板，固定在轴部的两个相对的两侧。 拉动部分具有驱动爪。 固定部件的驱动爪和止动板与棘轮啮合。

公开(公告)号：US6147372A

公开(公告)日：2000-11-14

申请号：US246293

申请日：1999-02-08

申请人： Hua-Yu Yang ,  Chih-Heng Shen ,  Wen-Cheng Chang

发明人： Hua-Yu Yang ,  Chih-Heng Shen ,  Wen-Cheng Chang

IPC分类号： H01L27/146 ,  H01L31/0352 ,  H01L27/148 ,  H01L29/768 ,  H01L29/80 ,  H01L31/112 ,  H01L31/288

CPC分类号： H01L31/0352 ,  H01L27/14603 ,  H01L27/14643

摘要： Device layouts are described which increase the photon current of a metal oxide semiconductor image sensor. The metal oxide semiconductor can be NMOS, PMOS, or CMOS. The key part of the photon current of the image sensors comes from the depletion region at the PN junction between the drain region and the substrate material. The layouts used significantly increase the area of this depletion region illuminated by a stream of photons. The layouts have a drain region which takes the shape of a number of parallel fingers perpendicular to the gate electrode, a number of parallel fingers parallel to the gate electrode, or a spiral. The drain regions of these layouts significantly increase the area of the drain depletion region illuminated by a stream of electrons.

摘要翻译： 描述了增加金属氧化物半导体图像传感器的光子电流的装置布局。 金属氧化物半导体可以是NMOS，PMOS或CMOS。 图像传感器的光子电流的关键部分来自漏极区域和衬底材料之间的PN结处的耗尽区。 使用的布局显着增加了由光子束照射的这个耗尽区域的面积。 布局具有漏极区域，其具有垂直于栅电极的多个平行指状物，平行于栅电极的多个平行指状物或螺旋形的形状。 这些布局的漏极区域显着地增加了由电子流照射的漏极耗尽区域的面积。

公开(公告)号：US06313516B1

公开(公告)日：2001-11-06

申请号：US09524523

申请日：2000-03-13

申请人： Yu-Ming Tsui ,  Wen-Cheng Chang ,  Shung-Jen Yu

发明人： Yu-Ming Tsui ,  Wen-Cheng Chang ,  Shung-Jen Yu

IPC分类号： H01L2900

CPC分类号： H01L28/20 ,  H01L27/0629

摘要： A high-sheet-resistance polysilicon resistor for integrated circuits is achieved by using a two-layer polysilicon process. After forming FET gate electrodes and capacitor bottom electrodes from a polycide layer, a thin interpolysilicon oxide (IPO) layer is deposited to form the capacitor interelectrode dielectric. A doped polysilicon layer and an undoped polysilicon layer are deposited and patterned to form the resistor. The doped polysilicon layer is in-situ doped to minimize the temperature and voltage coefficients of resistivity. Since the undoped polysilicon layer has a very high resistance (infinite), the resistance is predominantly determined by the doped polysilicon layer. The doped polysilicon layer can be reduced in thickness (less than 1000 Angstroms) to further increase the sheet resistance for mixed-mode circuits, while the undoped polysilicon layer allows contact openings to be etched in an insulating layer over the resistor without overetching the thin doped polysilicon layer and damaging the underlying IPO layer.

摘要翻译： 用于集成电路的高电阻多晶硅电阻器通过使用两层多晶硅工艺实现。 在从多晶硅层形成FET栅电极和电容器底电极之后，沉积薄的多晶硅氧化物（IPO）层以形成电容器电极间电介质。 沉积掺杂多晶硅层和未掺杂多晶硅层并构图以形成电阻器。 掺杂多晶硅层被原位掺杂以最小化电阻率的温度和电压系数。 由于未掺杂的多晶硅层具有非常高的电阻（无限大），所以电阻主要由掺杂多晶硅层决定。 掺杂多晶硅层可以减小厚度（小于1000埃），以进一步提高混合模式电路的薄层电阻，而未掺杂的多晶硅层允许在电阻器上的绝缘层中蚀刻接触开口，而不会过滤掉掺杂 多晶硅层，并损坏底层的IPO层。