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公开(公告)号：US09489877B2
公开(公告)日：2016-11-08
申请号：US14435466
申请日：2015-01-12
IPC: G09G3/00
CPC classification number: G09G3/006 , G09G2300/0426 , G09G2330/12
Abstract: A detecting circuit comprises a first to a third detecting line, a first and a second control line, and a first to a sixth transistor set. Each transistor set comprises a first and a second transistor, a control terminal thereof couples to the first and the second control line, respectively, a first terminal thereof couples to one of the first to the third detecting line, a second terminal thereof couples to the second terminal of the second transistor in the same transistor set. The connection nodes compose a dot set [(3,3), (2,2), (3,1), (2,3), (3,2), (2,1)], wherein the numerals 1-3 represent the first to the third detecting line, a first and a second numeral of a dot represent that a first terminal of the first and the second transistor connect to the detecting lines represented by the numerals, respectively.
Abstract translation: 检测电路包括第一至第三检测线，第一和第二控制线以及第一至第六晶体管组。 每个晶体管组包括第一和第二晶体管，其控制端分别耦合到第一和第二控制线，其第一端耦合到第一至第三检测线中的一个，其第二端耦合到 第二晶体管的第二端子位于同一晶体管组中。 连接节点组成点集[（3,3），（2,2），（3,1），（2,3），（3,2），（2,1）]，其中数字1- 3表示第一到第三检测线，点的第一和第二数字表示第一和第二晶体管的第一端子分别连接到由数字表示的检测线。
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公开(公告)号：US09224354B2
公开(公告)日：2015-12-29
申请号：US14234393
申请日：2013-12-18
Inventor： Cheng-Hung Chen , Jehao Hsu , Zui Wang , Xiaohui Yao
IPC: G09G3/36
CPC classification number: G09G3/3696 , G09G3/3648 , G09G3/3659 , G09G3/3677 , G09G2300/0426 , G09G2300/0443 , G09G2300/0447 , G09G2300/0465 , G09G2300/0814 , G09G2300/0852 , G09G2330/021 , G09G2330/04 , G09G2360/08
Abstract: A pixel driving method of a liquid crystal display (LCD) device, the LCD device comprising a first stage pixel, a second stage pixel, a first transistor, a second transistor, a third transistor, a first scan line, a second scan line, a plurality of data lines, a main pixel electrode, a sub pixel electrode, and a share capacitance, and the pixel driving method comprising the following steps: A step of driving the first scan line during the first driving period to charge the main pixel electrode and the sub pixel electrode of the first stage pixel, a step of ceasing to drive the first scan line during the second driving period to reduce voltages of the main pixel electrode and the sub pixel electrode of the first stage pixel, a step of driving the second scan line during the third driving period to turn on the third transistor of the first stage pixel, and a step of ceasing to drive the second scan line during the fourth driving period and pulling down the voltages of the main pixel electrode and the sub pixel electrode of the first stage pixel by implementing the share capacitance, which is connected with the third transistor during the third and the fourth driving period.
Abstract translation: 一种液晶显示器（LCD）器件的像素驱动方法，所述LCD器件包括第一级像素，第二级像素，第一晶体管，第二晶体管，第三晶体管，第一扫描线，第二扫描线， 多个数据线，主像素电极，子像素电极和共享电容，并且所述像素驱动方法包括以下步骤：在所述第一驱动周期期间驱动所述第一扫描线以对所述主像素电极充电的步骤 和第一级像素的子像素电极，在第二驱动周期期间停止驱动第一扫描线的步骤，以减少第一级像素的主像素电极和子像素电极的电压;驱动第 在第三驱动周期期间的第二扫描线，以接通第一级像素的第三晶体管，以及在第四驱动周期期间停止驱动第二扫描线并降低主像素电极的电压的步骤 通过实施在第三和第四驱动周期期间与第三晶体管连接的共享电容来实现第一级像素的子像素电极和子像素电极。
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公开(公告)号：US08896773B2
公开(公告)日：2014-11-25
申请号：US13642532
申请日：2012-09-25
Inventor： Zui Wang
IPC: G02F1/1335
CPC classification number: G02F1/136286 , G02F1/134309 , G02F2001/134345 , G02F2201/40
Abstract: The present invention provides an array of FPR 3D liquid crystal display, including a plurality of pixel units and circuit affecting on the pixel unit. The pixel unit is divided into main pixel area and sub pixel area, and the circuit is paid out between pixel units. The present invention also provides an FPR 3D liquid crystal display panel. As such, the present invention can improve opening ratio and penetration ratio of liquid crystal display panel in 3D display mode to increase luminance of liquid crystal display panel.
Abstract translation: 本发明提供一种FPR 3D液晶显示器阵列，其包括影响像素单元的多个像素单元和电路。 像素单元被划分为主像素区域和子像素区域，并且在像素单元之间支付电路。 本发明还提供一种FPR 3D液晶显示面板。 因此，本发明可以提高液晶显示面板在3D显示模式下的开口率和穿透率，以提高液晶显示面板的亮度。
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4.发明授权公开(公告)号：US09785026B2
公开(公告)日：2017-10-10
申请号：US14439216
申请日：2015-04-02
Inventor： Zui Wang
IPC: G02F1/1362 , G02F1/1333 , G02F1/1368 , G02F1/1343
CPC classification number: G02F1/136286 , G02F1/1333 , G02F1/133345 , G02F1/13439 , G02F1/1362 , G02F1/136213 , G02F1/136259 , G02F1/1368 , G02F2001/136263 , G02F2001/13629 , G02F2001/136295 , G02F2201/121 , G02F2201/123 , G02F2201/508
Abstract: The present invention provides a liquid crystal display device, a liquid crystal display, a manufacturing method and a darkening process. The liquid crystal display includes a lower substrate provided with a lower common electrode, a scanning line, a data line, a pixel electrode and a TFT. A gate electrode of the TFT is connected with the scanning line. A source electrode of the TFT is connected with a data line. A drain electrode of the TFT is connected with the pixel electrode. Wherein, the lower common electrode has an extension portion. A connection line of the data line and the source electrode of the TFT is spaced apart from and overlapped with the extension portion. When executing a darkening process, the connection line is disconnected from the data line, and connecting the extension portion and the connection line.
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5.发明授权公开(公告)号：US09523899B2
公开(公告)日：2016-12-20
申请号：US14423431
申请日：2015-02-06
Inventor： Zui Wang
IPC: G09G3/36 , G02F1/1362 , G02F1/1333 , G02F1/1343 , G02F1/1368
CPC classification number: G02F1/136259 , G02F1/133345 , G02F1/134309 , G02F1/13439 , G02F1/13624 , G02F1/136286 , G02F1/1368 , G02F2001/133302 , G02F2001/134345 , G02F2201/121 , G02F2201/123
Abstract: The present invention provides a pixel structure and a detection method of promoting defect detection rate. The pixel structure of promoting defect detection rate comprises two areas of a main pixel (10) and a sub pixel (20), and the sub pixel (20) comprises a charge sharing thin film transistor (T3) and a charge sharing capacitor (CST3); a gate of the charge sharing thin film transistor (T3) is electrically coupled to a charge sharing scan line (Gate2(m)); the charge sharing capacitor (CST3) is constructed by an ITO layer upper electrode plate (42), a metal lower electrode plate (2) and an insulative layer (3) sandwiched between the ITO layer upper electrode plate (42) and the metal lower electrode plate (2); the ITO layer upper electrode plate (42) and an ITO pixel electrode (41) are in a same layer, and the ITO layer upper electrode plate (42) is employed as a pixel common electrode coupled to a common voltage signal line (Com(m)), and the metal lower electrode plate (2) is coupled to a drain of the charge sharing thin film transistor (T3).
Abstract translation: 本发明提供了一种提高缺陷检测率的像素结构和检测方法。 促进缺陷检测率的像素结构包括主像素（10）和子像素（20）的两个区域，子像素（20）包括电荷共享薄膜晶体管（T3）和电荷共享电容器（CST3 ）; 电荷共享薄膜晶体管（T3）的栅极电耦合到电荷共享扫描线（Gate2（m））; 电荷共享电容器（CST3）由ITO层上电极板（42），金属下电极板（2）和夹在ITO层上电极板（42）和金属下电极板之间的绝缘层（3）构成 电极板（2）; ITO层上电极板（42）和ITO像素电极（41）处于同一层，ITO层上电极板（42）用作耦合到公共电压信号线（Com（ m）），并且金属下电极板（2）与电荷共享薄膜晶体管（T3）的漏极耦合。
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Patent Agency Ranking
公开(公告)号：US20160246125A1
公开(公告)日：2016-08-25
申请号：US14418179
申请日：2015-01-13
Inventor： Zui Wang
IPC: G02F1/1343 , H01L27/12 , G02F1/1333 , G02F1/1362 , G02F1/1335 , G02F1/1368
CPC classification number: G02F1/134309 , G02F1/133345 , G02F1/133514 , G02F1/13439 , G02F1/13624 , G02F1/136286 , G02F1/1368 , G02F2001/134345 , H01L27/124 , H01L27/1255
Abstract: An array substrate and a display device, which can solve the technical problem of short circuit of transparent electrode and the failure of detection thereof, are provided. In the array substrate, each pixel unit comprises a primary pixel electrode, a secondary pixel electrode, and a voltage dividing capacitor. The voltage dividing capacitor comprises a common terminal electrode and a voltage dividing terminal electrode. The primary pixel electrode, the secondary pixel electrode, and the common terminal electrode are located at the same layer.
Abstract translation: 提供了可以解决透明电极短路技术问题的阵列基板和显示装置及其检测失败。 在阵列基板中，每个像素单元包括主像素电极，次像素电极和分压电容器。 分压电容器包括公共端子电极和分压端子电极。 初级像素电极，次级像素电极和公共端子电极位于同一层。
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公开(公告)号：US20160124273A1
公开(公告)日：2016-05-05
申请号：US14408004
申请日：2014-11-19
IPC: G02F1/1343 , G02F1/1335 , G02F1/1368
CPC classification number: G02F1/134309 , G02F1/133514 , G02F2001/136218
Abstract: The present invention provides a curved display panel and a curved display apparatus. The curved display panel comprises a curved color filter substrate, a liquid crystal layer and a curved thin film transistor array substrate. The curved color filter substrate comprises a first curved substrate, a color-resisting array layer, a first protective layer and a common electrode; the curved thin film transistor array substrate comprises a second curved substrate and a pixel array layer. The present invention can diminish the dark fringes appearing in border areas of different domains.
Abstract translation: 本发明提供了一种弯曲显示面板和弯曲显示装置。 弯曲显示面板包括弯曲滤色器基板，液晶层和弯曲薄膜晶体管阵列基板。 弯曲滤色器基板包括第一弯曲基板，耐着色阵列层，第一保护层和公共电极; 弯曲的薄膜晶体管阵列基板包括第二弯曲基板和像素阵列层。 本发明可以减少出现在不同域的边界区域的黑色条纹。
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公开(公告)号：US20150170595A1
公开(公告)日：2015-06-18
申请号：US14234393
申请日：2013-12-18
Inventor： Cheng-Hung Chen , Jehao Hsu , Zui Wang , Xiaohui Yao
IPC: G09G3/36
CPC classification number: G09G3/3696 , G09G3/3648 , G09G3/3659 , G09G3/3677 , G09G2300/0426 , G09G2300/0443 , G09G2300/0447 , G09G2300/0465 , G09G2300/0814 , G09G2300/0852 , G09G2330/021 , G09G2330/04 , G09G2360/08
Abstract: A pixel driving method of a liquid crystal display (LCD) device, the LCD device comprising a first stage pixel, a second stage pixel, a first transistor, a second transistor, a third transistor, a first scan line, a second scan line, a plurality of data lines, a main pixel electrode, a sub pixel electrode, and a share capacitance, and the pixel driving method comprising the following steps: A step of driving the first scan line during the first driving period to charge the main pixel electrode and the sub pixel electrode of the first stage pixel, a step of ceasing to drive the first scan line during the second driving period to reduce voltages of the main pixel electrode and the sub pixel electrode of the first stage pixel, a step of driving the second scan line during the third driving period to turn on the third transistor of the first stage pixel, and a step of ceasing to drive the second scan line during the fourth driving period and pulling down the voltages of the main pixel electrode and the sub pixel electrode of the first stage pixel by implementing the share capacitance, which is connected with the third transistor during the third and the fourth driving period.
Abstract translation: 一种液晶显示器（LCD）器件的像素驱动方法，所述LCD器件包括第一级像素，第二级像素，第一晶体管，第二晶体管，第三晶体管，第一扫描线，第二扫描线， 多个数据线，主像素电极，子像素电极和共享电容，并且所述像素驱动方法包括以下步骤：在所述第一驱动周期期间驱动所述第一扫描线以对所述主像素电极充电的步骤 和第一级像素的子像素电极，在第二驱动周期期间停止驱动第一扫描线的步骤，以减少第一级像素的主像素电极和子像素电极的电压;驱动第 在第三驱动周期期间的第二扫描线，以接通第一级像素的第三晶体管，以及在第四驱动周期期间停止驱动第二扫描线并降低主像素电极的电压的步骤 通过实施在第三和第四驱动周期期间与第三晶体管连接的共享电容来实现第一级像素的子像素电极和子像素电极。
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9.发明申请Patterned Retarder 3D Liquid Crystal Display and the Manufacturing Method Thereof 有权图案化延迟器3D液晶显示器及其制造方法公开(公告)号：US20140247407A1
公开(公告)日：2014-09-04
申请号：US13696068
申请日：2012-10-17
Inventor： Cheng-hung Chen , Zui Wang
IPC: G02B27/26 , G02F1/13363 , G02F1/1335
CPC classification number: G02B27/26 , G02F1/1335 , G02F1/133512 , G02F1/13363 , G02F2001/133631 , H04N13/31
Abstract: A patterned retarder 3D liquid crystal display is disclosed. The liquid crystal display includes a display panel, a polarizer, and a patterned retarder film. The display panel includes a first substrate and a second substrate spaced apart from each other. The second substrate includes an up stutter and a down surface, and the up surface is farther to the first substrate than the down surface. A black matrix is arranged on the down surface of the second substrate. A mask is arranged on a first surface or the second surface of the polarizer. The first surface of the polarizer is adjacent to the patterned retarder film and the second surface of the polarizer is adjacent to the second substrate. The mask. corresponds to portions of the black matrix. In addition, a manufacturing method of the patterned retarder 3D liquid crystal display is also disclosed.
Abstract translation: 公开了一种图案化的延迟器3D液晶显示器。 液晶显示器包括显示面板，偏振器和图案化延迟膜。 显示面板包括彼此间隔开的第一基板和第二基板。 第二基板包括上端口和下表面，并且上表面比下表面更靠近第一基板。 黑色矩阵布置在第二基板的下表面上。 掩模布置在偏振器的第一表面或第二表面上。 偏振器的第一表面与图案化的延迟片相邻，偏振片的第二表面与第二衬底相邻。 面具。 对应于黑矩阵的部分。 此外，还公开了图案化延迟器3D液晶显示器的制造方法。
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公开(公告)号：US10558090B2
公开(公告)日：2020-02-11
申请号：US15577357
申请日：2017-11-22
Inventor： Zui Wang
IPC: G02F1/1339
Abstract: A liquid crystal display panel is provided and has a color filter substrate and an array substrate. The array substrate has a sealant coating region. A first metal wire is disposed on the sealant coating region. An insulating layer is disposed on the sealant coating region and is located above the first metal wire. A second metal wire is disposed on the sealant coating region and is located above the insulating layer. Via holes are defined in the insulating layer in the sealant coating region. The second metal wire is connected to the first metal wire through the via holes. A redundant spacer is formed on the sealant coating region and correspondingly covers the via holes.
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