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    Method to form, and structure of, a dual damascene interconnect device
    1.
    发明授权
    Method to form, and structure of, a dual damascene interconnect device 有权
    双镶嵌互连装置的形成和结构的方法

    公开(公告)号：US06252290B1

    公开(公告)日：2001-06-26

    申请号：US09425903

    申请日：1999-10-25

    申请人： Shyue Fong Quek ,  Ting Cheong Ang ,  Lap Chan ,  Sang Yee Loong

    发明人： Shyue Fong Quek ,  Ting Cheong Ang ,  Lap Chan ,  Sang Yee Loong

    IPC分类号： H01L2900

    CPC分类号： H01L21/7682 ,  H01L21/76807 ,  H01L21/76835 ,  H01L2221/1026

    摘要： A method of fabricating a dual damascene interconnect structure in a semiconductor device, comprises the following steps. A first level via photo sensitive dielectric layer is deposited and exposed over a semiconductor structure. A first level trench photo sensitive dielectric layer is deposited and exposed over the first via photo sensitive dielectric layer. The exposed first level via photo sensitive dielectric and trench photo sensitive dielectric layers are patterned and etched to form a first level dual damascene opening. The first level dual damascene opening comprises an integral first level via and metal line openings. A first level metal layer is deposited over the first level trench photo sensitive dielectric layer, filling the first level dual damascene opening. The first level metal layer is planarized to form at least one first level dual damascene interconnect having a first level horizontal metal line and a first level vertical via stack. The above steps are repeated n-1 times to form n-1 more dual damascene interconnects over the first level dual damascene interconnect where n is the number of interconnect levels desired. A passivation layer is deposited and patterned over the nth metal dual damascene interconnect layer to form openings in the passivation layer. The n number of via photo sensitive dielectric and trench photo sensitive dielectric layers are stripped and removed beneath the passivation layer openings and between the plurality of dual damascene structures wherein the portion of the via photo sensitive dielectric underneath the horizontal metal lines of the stripped trench photo sensitive dielectric layers remains.

    摘要翻译： 一种在半导体器件中制造双镶嵌互连结构的方法，包括以下步骤。 通过光敏电介质层的第一级沉积并暴露在半导体结构上。 第一级沟槽光电介质层被沉积并暴露在第一通孔光敏介电层上。 通过光敏电介质和沟槽光敏电介质层曝光的第一级被图案化和蚀刻以形成第一级双镶嵌开口。 第一级双镶嵌开口包括集成的第一级通孔和金属线开口。 第一级金属层沉积在第一级沟槽光敏介电层上，填充第一级双镶嵌开口。 第一级金属层被平坦化以形成具有第一级水平金属线和第一级垂直通孔叠层的至少一个第一级双镶嵌互连。 上述步骤重复n-1次，以在第一级双镶嵌互连上形成n-1个双镶嵌互连，其中n是所需的互连级数。 在第n个金属双镶嵌互连层上沉积并图案化钝化层，以在钝化层中形成开口。 在钝化层开口之下和多个双镶嵌结构之间剥离并除去n个通孔光敏电介质层和沟槽光敏介电层，其中通过光敏电介质的部分在剥离的沟槽照片的水平金属线下方 保持敏感的电介质层。

    Vertical source/drain contact semiconductor
    3.
    发明授权
    Vertical source/drain contact semiconductor 有权
    垂直源极/漏极接触半导体

    公开(公告)号：US06465296B1

    公开(公告)日：2002-10-15

    申请号：US10167095

    申请日：2002-06-10

    申请人： Shyue Fong Quek ,  Ting Cheong Ang ,  Sang Yee Loong ,  Puay Ing Ong

    发明人： Shyue Fong Quek ,  Ting Cheong Ang ,  Sang Yee Loong ,  Puay Ing Ong

    IPC分类号： H01L218238

    CPC分类号： H01L29/66772 ,  H01L21/76264 ,  H01L21/76281 ,  H01L29/41733 ,  H01L29/458 ,  H01L29/66636 ,  H01L29/66825 ,  H01L29/78621

    摘要： A semiconductor device and manufacturing process therefor is provided in which angled dopant implantation is followed by the formation of vertical trenches in the silicon on insulator substrate adjacent to the sides of the semiconductor gate. A second dopant implantation in the exposed the source/drain junctions is followed by a rapid thermal anneal that forms the semiconductor channel in the substrate. Contacts having inwardly curved cross-sectional widths in the semiconductor substrate are then formed which connect vertically to the exposed source/drain junctions either directly or through salicided contact areas.

    摘要翻译： 提供了一种半导体器件及其制造方法，其中倾斜的掺杂剂注入之后是在与半导体栅极的侧面相邻的绝缘体上硅衬底中形成垂直沟槽。 暴露在源极/漏极结中的第二掺杂剂注入之后是在衬底中形成半导体沟道的快速热退火。 然后形成在半导体衬底中具有向内弯曲的横截面宽度的触头，其直接地或通过咸水接触区域垂直连接到暴露的源极/漏极接合点。

    Triple-layered low dielectric constant dielectric dual damascene approach
    4.
    发明授权
    Triple-layered low dielectric constant dielectric dual damascene approach 有权
    三层低介电常数电介质双镶嵌方法

    公开(公告)号：US06406994B1

    公开(公告)日：2002-06-18

    申请号：US09726657

    申请日：2000-11-30

    申请人： Ting Cheong Ang ,  Shyue Fong Quek ,  Yee Chong Wong ,  Sang Yee Loong

    发明人： Ting Cheong Ang ,  Shyue Fong Quek ,  Yee Chong Wong ,  Sang Yee Loong

    IPC分类号： H01L2144

    CPC分类号： B41M5/5254 ,  B41M5/508 ,  B41M5/5218 ,  B41M5/5272 ,  Y10T428/24802

    摘要： A triple layered low dielectric constant material dual damascene metallization process is described. Metal lines are provided covered by an insulating layer overlying a semiconductor substrate. A first dielectric layer of a first type is deposited overlying the insulating layer. A second dielectric layer of a second type is deposited overlying the first dielectric layer. A via pattern is etched into the second dielectric layer. Thereafter, a third dielectric layer of the first type is deposited overlying the patterned second dielectric layer. Simultaneously, a trench pattern is etched into the third dielectric layer and the via pattern is etched into the first dielectric layer to complete the formation of dual damascene openings in the fabrication of an integrated circuit device. If the first type is a low dielectric constant organic material, the second type will be a low dielectric constant inorganic material. If the first type is a low dielectric constant inorganic material, the second type will be a low dielectric constant organic material.

    摘要翻译： 描述了三层低介电常数材料双镶嵌金属化工艺。 金属线被覆盖在半导体衬底上的绝缘层所覆盖。 第一类型的第一介电层沉积在绝缘层上。 第二类型的第二介电层沉积在第一介电层上。 通孔图案被蚀刻到第二介电层中。 此后，第一类型的第三电介质层沉积在图案化的第二介电层上。 同时，沟槽图案被蚀刻到第三介电层中，并且通孔图案被蚀刻到第一介电层中，以在集成电路器件的制造中完成双镶嵌开口的形成。 如果第一种类型是低介电常数有机材料，则第二种类型将是低介电常数无机材料。 如果第一种类型是低介电常数无机材料，则第二类型将是低介电常数有机材料。

    Method of body contact for SOI mosfet
    5.
    发明授权
    Method of body contact for SOI mosfet 有权
    SOI mosfet的身体接触方法

    公开(公告)号：US06787422B2

    公开(公告)日：2004-09-07

    申请号：US09755572

    申请日：2001-01-08

    申请人： Ting Cheong Ang ,  Sang Yee Loong ,  Shyue Fong Quek ,  Jun Song

    发明人： Ting Cheong Ang ,  Sang Yee Loong ,  Shyue Fong Quek ,  Jun Song

    IPC分类号： H01L21336

    CPC分类号： H01L29/66772 ,  H01L29/78615

    摘要： A new method for forming a silicon-on-insulator MOSFET while eliminating floating body effects is described. A silicon-on-insulator substrate is provided comprising a silicon semiconductor substrate underlying an oxide layer underlying a silicon layer. A first trench is etched partially through the silicon layer and not to the underlying oxide layer. Second trenches are etched fully through the silicon layer to the underlying oxide layer wherein the second trenches separate active areas of the semiconductor substrate and wherein one of the first trenches lies within each of the active areas. The first and second trenches are filled with an insulating layer. Gate electrodes and associated source and drain regions are formed in and on the silicon layer in each active area. An interlevel dielectric layer is deposited overlying the gate electrodes. First contacts are opened through the interlevel dielectric layer to the underlying source and drain regions. A second contact opening is made through the interlevel dielectric layer in each of the active regions wherein the second contact opening contacts both the first trench and one of the second trenches. The first and second contact openings are filled with a conducting layer to complete formation of a silicon-on-insulator device in the fabrication of integrated circuits.

    摘要翻译： 描述了一种在消除浮体效应的同时形成绝缘体上硅MOSFET的新方法。 提供了一种绝缘体上硅衬底，其包括位于硅层下面的氧化物层下面的硅半导体衬底。 第一沟槽部分地被蚀刻穿过硅层而不是蚀刻到下面的氧化物层。 第二沟槽被完全蚀刻通过硅层到下面的氧化物层，其中第二沟槽分离半导体衬底的有源区域，并且其中第一沟槽中的一个位于每个有源区域内。 第一和第二沟槽填充有绝缘层。 栅极电极和相关的源极和漏极区域形成在每个有源区域中的硅层中和硅层上。 沉积覆盖栅电极的层间电介质层。 第一触点通过层间介质层开放到下面的源极和漏极区域。 在每个有源区域中通过层间电介质层形成第二接触开口，其中第二接触开口接触第一沟槽和第二沟槽中的一个沟槽。 第一和第二接触开口填充有导电层，以在集成电路的制造中完成绝缘体上硅器件的形成。

    Alternating phase shift mask and method for fabricating the alignment monitor
    8.
    发明授权
    Alternating phase shift mask and method for fabricating the alignment monitor 有权
    交替相移掩模和制造对准监视器的方法

    公开(公告)号：US06416909B1

    公开(公告)日：2002-07-09

    申请号：US09618673

    申请日：2000-07-18

    申请人： Shyue Fong Quek ,  Ting Cheong Ang ,  Swee Hong Choo ,  Sang Yee Loong

    发明人： Shyue Fong Quek ,  Ting Cheong Ang ,  Swee Hong Choo ,  Sang Yee Loong

    IPC分类号： G03F900

    CPC分类号： G03F1/30 ,  G03F7/70216

    摘要： A new process for fabricating an alternating phase-shifting photomask having an alignment monitor is described. An opaque layer is provided overlying a substrate. The opaque layer is patterned to provide a mask pattern. A phase-shifting pattern is formed on the substrate wherein a portion of the phase-shifting pattern comprises an alignment monitor whereby alignment between the mask pattern and the phase-shifting pattern can be tested.

    摘要翻译： 描述了一种用于制造具有对准监视器的交替移相光掩模的新工艺。 覆盖在衬底上的不透明层被提供。 将不透明层图案化以提供掩模图案。 在基板上形成有一个移相图案，其中一部分移相图案包括对准监视器，从而可以测试掩模图案和移相图案之间的对准。

    Method of forming PID protection diode for SOI wafer
    9.
    发明授权
    Method of forming PID protection diode for SOI wafer 有权
    形成SOI晶圆的PID保护二极管的方法

    公开(公告)号：US06303414B1

    公开(公告)日：2001-10-16

    申请号：US09614558

    申请日：2000-07-12

    申请人： Ting Cheong Ang ,  Shyue Fong Quek ,  Sang Yee Loong ,  Jun Song

    发明人： Ting Cheong Ang ,  Shyue Fong Quek ,  Sang Yee Loong ,  Jun Song

    IPC分类号： H01L2100

    CPC分类号： H01L21/84 ,  H01L27/1203

    摘要： An integrated microelectronics semiconductor circuit fabricated on a silicon-on-insulator (SOI) type substrate can be protected from unwanted current surges and excessive heat buildup during fabrication by means of a heat-dissipating, protective plasma-induced-damage (PID) diode. The present invention fabricates such a protective diode as a part of the overall scheme in which the transistor devices are formed.

    摘要翻译： 在绝缘体上硅（SOI）型衬底上制造的集成微电子半导体电路可以通过散热，保护等离子体诱导损伤（PID）二极管在制造期间免受不必要的电流浪涌和过度积累热量。 本发明制造这样的保护二极管作为其中形成晶体管器件的整体方案的一部分。

    Method to fabricate a sub-quarter-micron MOSFET with lightly doped source/drain regions
    10.
    发明授权
    Method to fabricate a sub-quarter-micron MOSFET with lightly doped source/drain regions 失效
    制造具有轻掺杂源极/漏极区域的亚四分之一微米MOSFET的方法

    公开(公告)号：US06214680B1

    公开(公告)日：2001-04-10

    申请号：US09460111

    申请日：1999-12-13

    申请人： Shyue Fong Quek ,  Ting Cheong Ang ,  Puay Ink Ong ,  Sang Yee Loong

    发明人： Shyue Fong Quek ,  Ting Cheong Ang ,  Puay Ink Ong ,  Sang Yee Loong

    IPC分类号： H01L21336

    CPC分类号： H01L29/66492 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66545

    摘要： A new method of fabricating a MOSFET device is described. A semiconductor substrate is provided and isolation areas are formed isolating active areas in the substrate. An oxide layer is provided overlying both the substrate and isolation area and is patterned and etched to expose two areas within an isolated active area of the substrate. Selective epitaxial growth (SEG) using intrinsic silicon is performed to fill the exposed substrate areas formed in the previous etch step. The oxide layer region in the active area between the two epitaxially grown silicon regions is then etched, exposing the substrate. This is followed by a gate oxide growth and a polysilicon deposition. Planarization is then performed on the surface to expose the two epitaxially grown silicon regions. A second oxide is grown consuming some of the polysilicon gate and the epitaxially grown silicon. This consumption occurs at a higher rate at the upper surface and thus shapes the gate and epitaxially grown silicon into trapezoids with the base being wider than the top. The oxide is then etched leaving V-shaped trenches between the polysilicon and epitaxially grown silicon. A low-angle implantation is performed creating the source/drain extensions in the substrate below the V-shaped trenches. A third oxide is deposited filling the V-shaped groove and overlying the surface of the wafer. A second planarization is performed exposing the top of the epitaxially grown silicon regions and the polysilicon gate. A second implantation is performed to dope the polysilicon gate and epitaxially grown silicon regions. The doped portions of the epitaxially grown silicon form the source drain electrodes of the MOSFET. This is then followed by a salicidation step for metalization and annealing of the second implantation completing the MOSFET device.

    摘要翻译： 描述了一种制造MOSFET器件的新方法。 提供半导体衬底，并且形成隔离区域以隔离衬底中的有源区域。 提供覆盖衬底和隔离区域的氧化物层，并且被图案化和蚀刻以暴露衬底的隔离有效区域内的两个区域。 执行使用本征硅的选择性外延生长（SEG）以填充在先前蚀刻步骤中形成的暴露的衬底区域。 然后蚀刻两个外延生长的硅区域之间的有源区域中的氧化物层区域，暴露衬底。 之后是栅极氧化物生长和多晶硅沉积。 然后在表面上进行平面化以暴露两个外延生长的硅区域。 第二氧化物生长消耗一些多晶硅栅极和外延生长的硅。 这种消耗以较高的速率发生在上表面，因此将浇口和外延生长的硅形成为梯形，基部比顶部宽。 然后蚀刻氧化物，留下多晶硅和外延生长的硅之间的V形沟槽。 执行低角度注入，在V形沟槽下面的衬底中产生源极/漏极延伸部。 沉积填充V形槽并覆盖晶片表面的第三氧化物。 进行外延生长的硅区域和多晶硅栅极的顶部的第二平面化。 进行第二次注入以掺杂多晶硅栅极和外延生长的硅区域。 外延生长硅的掺杂部分形成MOSFET的源极漏极。 然后进行用于金属化和退火完成MOSFET器件的第二次注入的盐析步骤。