公开(公告)号：US06611024B2

公开(公告)日：2003-08-26

申请号：US09946981

申请日：2001-09-06

申请人： Ting Cheong Ang ,  Shyue Fong Quek ,  Sang Yee Loong ,  Jun Song

发明人： Ting Cheong Ang ,  Shyue Fong Quek ,  Sang Yee Loong ,  Jun Song

IPC分类号： H01L2701

CPC分类号： H01L21/84 ,  H01L27/1203

摘要： An integrated microelectronics semiconductor circuit fabricated on a silicon-on-insulator (SOI) type substrate can be protected from unwanted current surges and excessive heat buildup during fabrication by means of a heat-dissipating, protective plasma-induced-damage (PID) diode. The present invention fabricates such a protective diode as a part of the overall scheme in which the transistor devices are formed.

公开(公告)号：US06787422B2

公开(公告)日：2004-09-07

申请号：US09755572

申请日：2001-01-08

申请人： Ting Cheong Ang ,  Sang Yee Loong ,  Shyue Fong Quek ,  Jun Song

发明人： Ting Cheong Ang ,  Sang Yee Loong ,  Shyue Fong Quek ,  Jun Song

IPC分类号： H01L21336

CPC分类号： H01L29/66772 ,  H01L29/78615

摘要： A new method for forming a silicon-on-insulator MOSFET while eliminating floating body effects is described. A silicon-on-insulator substrate is provided comprising a silicon semiconductor substrate underlying an oxide layer underlying a silicon layer. A first trench is etched partially through the silicon layer and not to the underlying oxide layer. Second trenches are etched fully through the silicon layer to the underlying oxide layer wherein the second trenches separate active areas of the semiconductor substrate and wherein one of the first trenches lies within each of the active areas. The first and second trenches are filled with an insulating layer. Gate electrodes and associated source and drain regions are formed in and on the silicon layer in each active area. An interlevel dielectric layer is deposited overlying the gate electrodes. First contacts are opened through the interlevel dielectric layer to the underlying source and drain regions. A second contact opening is made through the interlevel dielectric layer in each of the active regions wherein the second contact opening contacts both the first trench and one of the second trenches. The first and second contact openings are filled with a conducting layer to complete formation of a silicon-on-insulator device in the fabrication of integrated circuits.

摘要翻译： 描述了一种在消除浮体效应的同时形成绝缘体上硅MOSFET的新方法。 提供了一种绝缘体上硅衬底，其包括位于硅层下面的氧化物层下面的硅半导体衬底。 第一沟槽部分地被蚀刻穿过硅层而不是蚀刻到下面的氧化物层。 第二沟槽被完全蚀刻通过硅层到下面的氧化物层，其中第二沟槽分离半导体衬底的有源区域，并且其中第一沟槽中的一个位于每个有源区域内。 第一和第二沟槽填充有绝缘层。 栅极电极和相关的源极和漏极区域形成在每个有源区域中的硅层中和硅层上。 沉积覆盖栅电极的层间电介质层。 第一触点通过层间介质层开放到下面的源极和漏极区域。 在每个有源区域中通过层间电介质层形成第二接触开口，其中第二接触开口接触第一沟槽和第二沟槽中的一个沟槽。 第一和第二接触开口填充有导电层，以在集成电路的制造中完成绝缘体上硅器件的形成。

公开(公告)号：US06303414B1

公开(公告)日：2001-10-16

申请号：US09614558

申请日：2000-07-12

申请人： Ting Cheong Ang ,  Shyue Fong Quek ,  Sang Yee Loong ,  Jun Song

发明人： Ting Cheong Ang ,  Shyue Fong Quek ,  Sang Yee Loong ,  Jun Song

IPC分类号： H01L2100

CPC分类号： H01L21/84 ,  H01L27/1203

摘要： An integrated microelectronics semiconductor circuit fabricated on a silicon-on-insulator (SOI) type substrate can be protected from unwanted current surges and excessive heat buildup during fabrication by means of a heat-dissipating, protective plasma-induced-damage (PID) diode. The present invention fabricates such a protective diode as a part of the overall scheme in which the transistor devices are formed.

摘要翻译： 在绝缘体上硅（SOI）型衬底上制造的集成微电子半导体电路可以通过散热，保护等离子体诱导损伤（PID）二极管在制造期间免受不必要的电流浪涌和过度积累热量。 本发明制造这样的保护二极管作为其中形成晶体管器件的整体方案的一部分。

公开(公告)号：US06258677B1

公开(公告)日：2001-07-10

申请号：US09409875

申请日：1999-10-01

申请人： Ting Cheong Ang ,  Shyue Fong Quek ,  Sang Yee Loong ,  Jun Song

发明人： Ting Cheong Ang ,  Shyue Fong Quek ,  Sang Yee Loong ,  Jun Song

IPC分类号： H01L21336

CPC分类号： H01L29/0847 ,  H01L21/76264 ,  H01L21/76278 ,  H01L21/76283 ,  H01L21/823878 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66651

摘要： A method of fabricating a transistor, comprising the following steps. A silicon semiconductor structure having spaced, raised, wedge-shaped dielectric isolation regions defining an active region there between is provided. Epitaxial silicon is grown over the active area to form an SEG region. A dummy gate is formed over the SEG region. Raised epitaxial silicon layers are grown over the SEG region adjacent the dummy gate. The dummy gate is removed, exposing the interior side walls of the raised epitaxial silicon layers. Sidewall spacers are formed on the exposed sidewalls of the raised epitaxial silicon layers. A gate oxide layer is grown over the SEG region and between the sidewall spacers of the raised epitaxial silicon layers. A layer of polysilicon is deposited over the structure and is planarized to form a gate conductor over the SEG region and between the sidewall spacers of the raised epitaxial silicon layers. The sidewall spacers are removed. No HDP process trench fill is required to form the STIs and no CMP process is required to planarized the STIs.

摘要翻译： 一种制造晶体管的方法，包括以下步骤。 提供了具有限定其间的有源区域的具有间隔开的凸起的楔形介电隔离区域的硅半导体结构。 在活性区域上生长外延硅以形成SEG区域。 在SEG区域上形成一个虚拟门。 凸起的外延硅层生长在与虚拟栅极相邻的SEG区域上。 去除虚拟栅极，暴露凸起的外延硅层的内侧壁。 在凸起的外延硅层的暴露的侧壁上形成侧壁间隔物。 栅极氧化物层生长在SEG区域上并且在凸起的外延硅层的侧壁间隔物之间​​。 在该结构上沉积一层多晶硅，并将其平坦化，以在SEG区域和凸出的外延硅层的侧壁间隔物之间​​形成栅极导体。 去除侧壁间隔物。 不需要HDP工艺沟槽填充来形成STI，并且不需要CMP工艺来平坦化STI。

公开(公告)号：US06963113B2

公开(公告)日：2005-11-08

申请号：US10915670

申请日：2004-08-10

申请人： Ting Cheong Ang ,  Sang Yee Loong ,  Shyue Fong Quek ,  Jun Song

发明人： Ting Cheong Ang ,  Sang Yee Loong ,  Shyue Fong Quek ,  Jun Song

IPC分类号： H01L21/336 ,  H01L29/786 ,  H01L29/76

CPC分类号： H01L29/66772 ,  H01L29/78615

摘要： A new method for forming a silicon-on-insulator MOSFET while eliminating floating body effects is described. A silicon-on-insulator substrate is provided comprising a silicon semiconductor substrate underlying an oxide layer underlying a silicon layer. A first trench is etched partially through the silicon layer and not to the underlying oxide layer. Second trenches are etched fully through the silicon layer to the underlying oxide layer wherein the second trenches separate active areas of the semiconductor substrate and wherein one of the first trenches lies within each of the active areas. The first and second trenches are filled with an insulating layer. Gate electrodes and associated source and drain regions are formed in and on the silicon layer in each active area. An interlevel dielectric layer is deposited overlying the gate electrodes. First contacts are opened through the interlevel dielectric layer to the underlying source and drain regions. A second contact opening is made through the interlevel dielectric layer in each of the active regions wherein the second contact opening contacts both the first trench and one of the second trenches. The first and second contact openings are filled with a conducting layer to complete formation of a silicon-on-insulator device in the fabrication of integrated circuits.

摘要翻译： 描述了一种在消除浮体效应的同时形成绝缘体上硅MOSFET的新方法。 提供了一种绝缘体上硅衬底，其包括位于硅层下面的氧化物层下面的硅半导体衬底。 第一沟槽部分地被蚀刻穿过硅层而不是蚀刻到下面的氧化物层。 第二沟槽被完全蚀刻通过硅层到下面的氧化物层，其中第二沟槽分离半导体衬底的有源区域，并且其中第一沟槽中的一个位于每个有源区域内。 第一和第二沟槽填充有绝缘层。 栅极电极和相关的源极和漏极区域形成在每个有源区域中的硅层中和硅层上。 沉积覆盖栅电极的层间电介质层。 第一触点通过层间介质层开放到下面的源极和漏极区域。 在每个有源区域中通过层间电介质层形成第二接触开口，其中第二接触开口接触第一沟槽和第二沟槽中的一个沟槽。 第一和第二接触开口填充有导电层，以在集成电路的制造中完成绝缘体上硅器件的形成。

公开(公告)号：US06582856B1

公开(公告)日：2003-06-24

申请号：US09513872

申请日：2000-02-28

申请人： Shyue Fong Quek ,  Ting Cheong Ang ,  Jun Song ,  Sang Yee Loong

发明人： Shyue Fong Quek ,  Ting Cheong Ang ,  Jun Song ,  Sang Yee Loong

IPC分类号： G03F900

CPC分类号： G03F1/29

摘要： A new method of fabricating a rim phase shifting mask is achieved. An opaque layer is provided overlying a transparent substrate. A resist layer is deposited overlying the opaque layer. The resist layer is patterned. The opaque layer and the transparent substrate are etched. The resist layer masks this etching. The opaque layer is etched through during this etching. Notches are thereby etched into the transparent substrate at the edges of the opaque layer. These notches will cause a phase shift in incident light relative to incident light passing through regions in the transparent substrate adjacent to the notches. During this etching, an overetch is performed to remove any mask defects in the transparent substrate. Optionally, the notches may be etched into a phase shifting layer overlying the transparent substrate. An etch stopping layer may also be used in the phase shifting layer embodiment.

摘要翻译： 实现了制作边缘相移掩模的新方法。 在透明基底上方设置不透明层。 将抗蚀剂层沉积在不透明层上。 抗蚀剂层被图案化。 蚀刻不透明层和透明基板。 抗蚀剂层掩盖该蚀刻。 在该蚀刻期间蚀刻不透明层。 因此，在不透明层的边缘处，凹口被蚀刻到透明基板中。 这些凹口将引起入射光相对于穿过透明衬底中与凹口相邻的区域的入射光的相移。 在该蚀刻期间，执行过蚀刻以去除透明基板中的任何掩模缺陷。 可选地，凹口可被蚀刻到覆盖透明衬底的相移层中。 在相移层实施例中也可以使用蚀刻停止层。

公开(公告)号：US06764914B2

公开(公告)日：2004-07-20

申请号：US10290130

申请日：2002-11-07

申请人： Alex See ,  Cher Liang Randall Cha ,  Shyue Fong Quek ,  Ting Cheong Ang ,  Wye Boon Loh ,  Sang Yee Loong ,  Jun Song ,  Chua Chee Tee

发明人： Alex See ,  Cher Liang Randall Cha ,  Shyue Fong Quek ,  Ting Cheong Ang ,  Wye Boon Loh ,  Sang Yee Loong ,  Jun Song ,  Chua Chee Tee

IPC分类号： H01L2120

CPC分类号： H01L28/40 ,  H01L21/31683

摘要： A process for forming a high dielectric constant, (High K), layer, for a metal-oxide-metal, capacitor structure, featuring localized oxidation of an underlying metal layer, performed at a temperature higher than the temperature experienced by surrounding structures, has been developed. A first iteration of this process features the use of a laser ablation procedure, performed to a local region of an underlying metal layer, in an oxidizing ambient. The laser ablation procedure creates the desired, high temperature, only at the laser spot, allowing a high K layer to be created at this temperature, while the surrounding structures on a semiconductor substrate, not directly exposed to the laser ablation procedure remain at lower temperatures. A second iteration features the exposure of specific regions of an underlying metal layer, to a UV, or to an I line exposure procedure, performed in an oxidizing ambient, with the regions of an underlying metal layer exposed to the UV or I line procedure, via clear regions in an overlying photolithographic plate. This procedure also results in the formation of a high K layer, on a top portion of the underlying metal layer.

摘要翻译： 在高于周围结构所经历的温度的温度下进行的金属氧化物 - 金属电容器结构的高介电常数（高K）层，其特征在于底层金属层的局部氧化， 已经开发 该方法的第一次迭代的特征在于在氧化环境中使用对底层金属层的局部区域进行的激光烧蚀程序。 激光烧蚀过程仅在激光点产生所需的高温，允许在该温度下产生高K层，而不直接暴露于激光烧蚀过程的半导体衬底上的周围结构保持在较低温度 。 第二次迭代的特征在于在氧化环境中进行的底层金属层的特定区域到UV或I线曝光程序，暴露于UV或I线程序的下面的金属层的区域， 通过覆盖光刻板中的透明区域。 该过程还导致在下面的金属层的顶部上形成高K层。

公开(公告)号：US06399431B1

公开(公告)日：2002-06-04

申请号：US09531786

申请日：2000-03-21

申请人： Jun Song ,  Ting Cheong Ang ,  Shyue Fong Quek ,  Sang Yee Loong

发明人： Jun Song ,  Ting Cheong Ang ,  Shyue Fong Quek ,  Sang Yee Loong

IPC分类号： H01L2170

CPC分类号： H01L21/84 ,  H01L27/0266 ,  H01L27/1203 ,  H01L29/78603

摘要： A method for forming an electrostatic discharge device using silicon-on-insulator technology is described. A silicon-on-insulator substrate is provided comprising a semiconductor substrate underlying an oxide layer underlying a silicon layer. The silicon layer and oxide layer are patterned to form a gate electrode wherein the semiconductor substrate is exposed. Ions are implanted into the exposed semiconductor substrate to form source and drain regions adjacent to the gate electrode. Spacers are formed on sidewalls of the gate electrode. An interlevel dielectric layer is deposited overlying the gate electrode. Openings are formed through the interlevel dielectric layer to the source and drain regions and filled with a conducting layer. The conducting layer is patterned to form conducting lines to complete formation of an electrostatic discharge device using SOI technology in the fabrication of integrated circuits.

摘要翻译： 描述了使用绝缘体上硅技术形成静电放电装置的方法。 提供了一种绝缘体上硅衬底，其包括位于硅层下面的氧化物层下方的半导体衬底。 图案化硅层和氧化物层以形成其中暴露半导体衬底的栅电极。 将离子注入到暴露的半导体衬底中以形成与栅电极相邻的源区和漏区。 隔板形成在栅电极的侧壁上。 沉积在栅电极上的层间电介质层。 开口通过层间介电层形成到源区和漏区，并填充有导电层。 图案化导电层以形成导线，以在集成电路的制造中使用SOI技术完成静电放电装置的形成。

公开(公告)号：US06376379B1

公开(公告)日：2002-04-23

申请号：US09495344

申请日：2000-02-01

申请人： Shyue Fong Quek ,  Ting Cheong Ang ,  Jun Song ,  Sang Yee Loong

发明人： Shyue Fong Quek ,  Ting Cheong Ang ,  Jun Song ,  Sang Yee Loong

IPC分类号： H01L21302

CPC分类号： H01L21/31144 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/32139 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76829

摘要： A method of patterning a hard mask, the comprising the following steps. A semiconductor structure is provided. A conductor film is formed over the semiconductor structure. An oxide layer is formed over the conductor film. A patterned metal oxide layer is formed over the conductor film. The oxide layer and the conductor film are etched, using the metal oxide layer as a hard mask, to form a patterned structure.

摘要翻译： 图案化硬掩模的方法，包括以下步骤。 提供半导体结构。 在半导体结构上形成导体膜。 在导体膜上形成氧化物层。 在导体膜上形成图案化的金属氧化物层。 使用金属氧化物层作为硬掩模来蚀刻氧化物层和导体膜，以形成图案化结构。

公开(公告)号：US06465296B1

公开(公告)日：2002-10-15

申请号：US10167095

申请日：2002-06-10

申请人： Shyue Fong Quek ,  Ting Cheong Ang ,  Sang Yee Loong ,  Puay Ing Ong

发明人： Shyue Fong Quek ,  Ting Cheong Ang ,  Sang Yee Loong ,  Puay Ing Ong

IPC分类号： H01L218238

CPC分类号： H01L29/66772 ,  H01L21/76264 ,  H01L21/76281 ,  H01L29/41733 ,  H01L29/458 ,  H01L29/66636 ,  H01L29/66825 ,  H01L29/78621

摘要： A semiconductor device and manufacturing process therefor is provided in which angled dopant implantation is followed by the formation of vertical trenches in the silicon on insulator substrate adjacent to the sides of the semiconductor gate. A second dopant implantation in the exposed the source/drain junctions is followed by a rapid thermal anneal that forms the semiconductor channel in the substrate. Contacts having inwardly curved cross-sectional widths in the semiconductor substrate are then formed which connect vertically to the exposed source/drain junctions either directly or through salicided contact areas.

摘要翻译： 提供了一种半导体器件及其制造方法，其中倾斜的掺杂剂注入之后是在与半导体栅极的侧面相邻的绝缘体上硅衬底中形成垂直沟槽。 暴露在源极/漏极结中的第二掺杂剂注入之后是在衬底中形成半导体沟道的快速热退火。 然后形成在半导体衬底中具有向内弯曲的横截面宽度的触头，其直接地或通过咸水接触区域垂直连接到暴露的源极/漏极接合点。