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    Performance enhancement in PFET transistors comprising high-k metal gate stack by increasing dopant confinement
    3.
    发明授权
    Performance enhancement in PFET transistors comprising high-k metal gate stack by increasing dopant confinement 有权
    通过增加掺杂剂约束，包括高k金属栅极堆叠的PFET晶体管的性能增强

    公开(公告)号：US08404550B2

    公开(公告)日：2013-03-26

    申请号：US12905383

    申请日：2010-10-15

    申请人： Thilo Scheiper ,  Sven Beyer ,  Andy Wei ,  Jan Hoentschel

    发明人： Thilo Scheiper ,  Sven Beyer ,  Andy Wei ,  Jan Hoentschel

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7848 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66651

    摘要： In a P-channel transistor comprising a high-k metal gate electrode structure, a superior dopant profile may be obtained, at least in the threshold adjusting semiconductor material, such as a silicon/germanium material, by incorporating a diffusion blocking species, such as fluorine, prior to forming the threshold adjusting semiconductor material. Consequently, the drain and source extension regions may be provided with a high dopant concentration as required for obtaining the target Miller capacitance without inducing undue dopant diffusion below the threshold adjusting semiconductor material, which may otherwise result in increased leakage currents and increased risk of punch through events.

    摘要翻译： 在包含高k金属栅电极结构的P沟道晶体管中，至少在阈值调节半导体材料（例如硅/锗材料）中可以通过掺入扩散阻挡物质获得优异的掺杂剂分布，例如 在形成阈值调节半导体材料之前。 因此，漏极和源极延伸区域可以被提供有高的掺杂剂浓度，以获得目标米勒电容，而不会导致低于阈值调节半导体材料的不适当的掺杂剂扩散，否则可能导致增加的漏电流和增加的穿孔风险 事件

    Dual Cavity Etch for Embedded Stressor Regions
    4.
    发明申请
    Dual Cavity Etch for Embedded Stressor Regions 审中-公开
    嵌入式应力区域的双腔蚀刻

    公开(公告)号：US20120292637A1

    公开(公告)日：2012-11-22

    申请号：US13109134

    申请日：2011-05-17

    申请人： Sven Beyer ,  Peter Baars ,  Jan Hoentschel ,  Thilo Scheiper

    发明人： Sven Beyer ,  Peter Baars ,  Jan Hoentschel ,  Thilo Scheiper

    IPC分类号： H01L27/092 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/20

    CPC分类号： H01L21/823807 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/823814 ,  H01L21/84 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

    摘要： Generally, the present disclosure is directed to methods for forming embedded stressor regions in semiconductor devices such as transistor elements and the like. One illustrative method disclosed herein includes forming a first material in first cavities formed in a first active area adjacent to a first channel region of a semiconductor device, wherein the first material induces a first stress in the first channel region. The method also includes, among other things, forming a second material in second cavities formed in a second active area adjacent to a second channel region of the semiconductor device, wherein the second material induces a second stress in the second channel region that is of an opposite type of the first stress in the first channel region, and wherein the first and second cavities are formed during a common etch process.

    摘要翻译： 通常，本公开涉及在诸如晶体管元件等的半导体器件中形成嵌入的应力源区域的方法。 本文公开的一种说明性方法包括在与半导体器件的第一沟道区相邻的第一有源区中形成的第一空腔中形成第一材料，其中第一材料在第一沟道区域中引起第一应力。 该方法还包括在形成在与半导体器件的第二沟道区相邻的第二有源区中的第二腔中形成第二材料，其中第二材料在第二沟道区域中引起第二应力 在第一通道区域中相反类型的第一应力，并且其中第一和第二空腔在公共蚀刻工艺期间形成。

    WORK FUNCTION ADJUSTMENT IN HIGH-K GATE STACKS FOR DEVICES OF DIFFERENT THRESHOLD VOLTAGE
    7.
    发明申请
    WORK FUNCTION ADJUSTMENT IN HIGH-K GATE STACKS FOR DEVICES OF DIFFERENT THRESHOLD VOLTAGE 有权
    用于不同阈值电压器件的高K栅极堆栈中的工作功能调整

    公开(公告)号：US20110127616A1

    公开(公告)日：2011-06-02

    申请号：US12905501

    申请日：2010-10-15

    申请人： Jan Hoentschel ,  Sven Beyer ,  Thilo Scheiper

    发明人： Jan Hoentschel ,  Sven Beyer ,  Thilo Scheiper

    IPC分类号： H01L27/088 ,  H01L21/336

    CPC分类号： H01L21/28176 ,  H01L21/823857 ,  H01L29/517

    摘要： In sophisticated semiconductor devices, different threshold voltage levels for transistors may be set in an early manufacturing stage, i.e., prior to patterning the gate electrode structures, by using multiple diffusion processes and/or gate dielectric materials. In this manner, substantially the same gate layer stacks, i.e., the same electrode materials and the same dielectric cap materials, may be used, thereby providing superior patterning uniformity when applying sophisticated etch strategies.

    摘要翻译： 在复杂的半导体器件中，可以在早期制造阶段，即在通过使用多个扩散工艺和/或栅极电介质材料图案化栅极电极结构之前，将晶体管的不同阈值电压电平设置。 以这种方式，可以使用基本相同的栅极层堆叠，即相同的电极材料和相同的电介质盖材料，从而在应用复杂的蚀刻策略时提供优异的图案均匀性。

    Strain memorization in strained SOI substrates of semiconductor devices
    8.
    发明授权
    Strain memorization in strained SOI substrates of semiconductor devices 有权
    半导体器件的应变SOI衬底中的应变记忆

    公开(公告)号：US08329531B2

    公开(公告)日：2012-12-11

    申请号：US12917870

    申请日：2010-11-02

    申请人： Jan Hoentschel ,  Sven Beyer ,  Uwe Griebenow ,  Thilo Scheiper

    发明人： Jan Hoentschel ,  Sven Beyer ,  Uwe Griebenow ,  Thilo Scheiper

    IPC分类号： H01L21/8238 ,  H01L21/76 ,  H01L21/36 ,  H01L21/4763 ,  H01L21/311 ,  H01L21/469

    CPC分类号： H01L21/3081 ,  H01L21/76224 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/7849

    摘要： In sophisticated semiconductor devices, the initial strain component of a globally strained semiconductor layer may be substantially preserved during the formation of shallow trench isolations by using a rigid mask material, which may efficiently avoid or reduce a deformation of the semiconductor islands upon patterning the isolation trenches. Consequently, selected regions with high internal stress levels may be provided, irrespective of the height-to-length aspect ratio, which may limit the application of globally strained semiconductor layers in conventional approaches. Furthermore, in some illustrative embodiments, active regions of substantially relaxed strain state or of inverse strain type may be provided in addition to the highly strained active regions, thereby enabling an efficient process strategy for forming complementary transistors.

    摘要翻译： 在复杂的半导体器件中，通过使用刚性掩模材料可以在形成浅沟槽隔离期间实质上保留全局应变半导体层的初始应变分量，这可以有效地避免或减少图案化隔离沟槽时半导体岛的变形 。 因此，可以提供具有高内应力水平的选定区域，而不考虑高度 - 长度的纵横比，这可能限制在常规方法中全局应变半导体层的应用。 此外，在一些说明性实施例中，除了高应变活性区域之外，还可以提供基本上松弛的应变状态或逆应变类型的有源区，从而实现用于形成互补晶体管的有效的工艺策略。

    Patterning of a Stressed Dielectric Material in a Contact Level Without Using an Underlying Etch Stop Layer
    9.
    发明申请
    Patterning of a Stressed Dielectric Material in a Contact Level Without Using an Underlying Etch Stop Layer 审中-公开
    在不使用底层蚀刻停止层的情况下，接触层中的压电介电材料的图案化

    公开(公告)号：US20120156839A1

    公开(公告)日：2012-06-21

    申请号：US13191870

    申请日：2011-07-27

    申请人： Thilo Scheiper ,  Sven Beyer ,  Jan Hoentschel ,  Stefan Flachowsky

    发明人： Thilo Scheiper ,  Sven Beyer ,  Jan Hoentschel ,  Stefan Flachowsky

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823878

    摘要： An efficient strain-inducing mechanism may be implemented in the form of differently stressed material layers that are formed above transistors of different types. The strain-inducing dielectric materials may be formed so as to be in direct contact with the corresponding transistors, thereby enhancing the overall strain transfer efficiency. Moreover, the disclosed manufacturing strategy avoids or at least significantly reduces any interaction of reactive etch atmospheres used to pattern the strain-inducing material layers with metal silicide regions, which may be formed individually for each type of transistor.

    摘要翻译： 可以以不同类型的晶体管上形成的不同应力材料层的形式实施有效的应变诱导机构。 应变诱导电介质材料可以形成为与相应的晶体管直接接触，从而提高总的应变转移效率。 此外，所公开的制造策略避免或至少显着减少用于将应变诱导材料层图案化为金属硅化物区域的反应性蚀刻气氛的任何相互作用，金属硅化物区域可以针对每种类型的晶体管单独形成。