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1.发明授权Transistor including a high-K metal gate electrode structure formed prior to drain/source regions on the basis of a sacrificial carbon spacer 有权晶体管包括在牺牲碳间隔物的基础上在漏/源区之前形成的高K金属栅电极结构公开(公告)号：US07943462B1
公开(公告)日：2011-05-17
申请号：US12894579
申请日：2010-09-30
申请人： Sven Beyer , Thilo Scheiper , Jan Hoentschel , Markus Lenski
发明人： Sven Beyer , Thilo Scheiper , Jan Hoentschel , Markus Lenski
IPC分类号： H01L21/8238 , H01L21/8234 , H01L21/336
CPC分类号： H01L21/28238 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/51 , H01L29/665 , H01L29/6659 , H01L29/7833 , H01L29/7848
摘要： When forming sophisticated high-k metal gate electrode structures in an early manufacturing stage, the dielectric cap layer of the gate electrode structures may be efficiently removed on the basis of a carbon spacer element, which may thus preserve the integrity of the silicon nitride spacer structure. Thereafter, the sacrificial carbon spacer may be removed substantially without affecting other device areas, such as isolation structures, active regions and the like, which may contribute to superior process conditions during the further processing of the semiconductor device.
摘要翻译： 当在早期制造阶段形成复杂的高k金属栅电极结构时，可以基于碳间隔元件有效地去除栅电极结构的电介质盖层，这可以保持氮化硅间隔结构的完整性 。 此后，可以基本上除去牺牲碳隔离物而不影响其它器件区域，例如隔离结构，有源区等，这可能有助于在半导体器件的进一步处理期间优良的工艺条件。
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2.发明申请TRANSISTOR INCLUDING A HIGH-K METAL GATE ELECTRODE STRUCTURE FORMED PRIOR TO DRAIN/SOURCE REGIONS ON THE BASIS OF A SACRIFICIAL CARBON SPACER 有权包括在基于碳酸盐空间的排水/源区域形成的高K金属电极结构的晶体管公开(公告)号：US20110104863A1
公开(公告)日：2011-05-05
申请号：US12894579
申请日：2010-09-30
申请人： Sven Beyer , Thilo Scheiper , Jan Hoentschel , Markus Lenski
发明人： Sven Beyer , Thilo Scheiper , Jan Hoentschel , Markus Lenski
IPC分类号： H01L21/336
CPC分类号： H01L21/28238 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/51 , H01L29/665 , H01L29/6659 , H01L29/7833 , H01L29/7848
摘要： When forming sophisticated high-k metal gate electrode structures in an early manufacturing stage, the dielectric cap layer of the gate electrode structures may be efficiently removed on the basis of a carbon spacer element, which may thus preserve the integrity of the silicon nitride spacer structure. Thereafter, the sacrificial carbon spacer may be removed substantially without affecting other device areas, such as isolation structures, active regions and the like, which may contribute to superior process conditions during the further processing of the semiconductor device.
摘要翻译： 当在早期制造阶段形成复杂的高k金属栅电极结构时，可以基于碳间隔元件有效地去除栅电极结构的电介质盖层，这可以保持氮化硅间隔结构的完整性 。 此后，可以基本上除去牺牲碳隔离物而不影响其它器件区域，例如隔离结构，有源区等，这可能有助于在半导体器件的进一步处理期间优良的工艺条件。
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3.发明授权Technique for enhancing stress transfer into channel regions of NMOS and PMOS transistors 有权用于增强应力传递到NMOS和PMOS晶体管的沟道区域的技术公开(公告)号：US07344984B2
公开(公告)日：2008-03-18
申请号：US11468450
申请日：2006-08-30
申请人： Jan Hoentschel , Andy Wei , Markus Lenski , Peter Javorka
发明人： Jan Hoentschel , Andy Wei , Markus Lenski , Peter Javorka
IPC分类号： H01L21/44 , H01L21/4763
CPC分类号： H01L21/823864 , H01L21/823807 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/7843
摘要： A method and a semiconductor device are provided in which respective contact layers having a specific intrinsic stress may be directly formed on respective metal silicide regions without undue metal silicide degradation during an etch process for removing an unwanted portion of an initially deposited contact layer. Moreover, due to the inventive concept, the strain-inducing contact layers may be formed directly on the respective substantially L-shaped spacer elements, thereby enhancing even more the stress transfer mechanism.
摘要翻译： 提供了一种方法和半导体器件，其中具有特定固有应力的各个接触层可以直接形成在各自的金属硅化物区域上，而在用于去除最初沉积的接触层的不希望的部分的蚀刻工艺期间不会有不适当的金属硅化物降解。 此外，由于本发明构思，应变感应接触层可以直接形成在相应的大致L形间隔元件上，从而进一步增强应力传递机构。
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4.发明申请HIGH-K METAL GATE ELECTRODE STRUCTURES FORMED BY SEPARATE REMOVAL OF PLACEHOLDER MATERIALS IN TRANSISTORS OF DIFFERENT CONDUCTIVITY TYPE 审中-公开通过单独去除不同电导率晶体管中的位置材料形成的高K金属电极结构公开(公告)号：US20110101470A1
公开(公告)日：2011-05-05
申请号：US12894746
申请日：2010-09-30
申请人： Klaus Hempel , Sven Beyer , Markus Lenski , Stephan Kruegel
发明人： Klaus Hempel , Sven Beyer , Markus Lenski , Stephan Kruegel
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/28088 , H01L21/28026 , H01L21/823807 , H01L21/823842 , H01L21/82385 , H01L29/66545 , H01L29/66583 , H01L29/7833 , H01L29/7843
摘要： In a replacement gate approach, a superior cross-sectional shape of the gate opening may be achieved by performing a material erosion process in an intermediate state of removing the placeholder material. Consequently, the remaining portion of the placeholder material may efficiently protect the underlying sensitive materials, such as a high-k dielectric material, when performing the corner rounding process sequence.
摘要翻译： 在替代浇口方法中，可以通过在去除占位材料的中间状态下进行材料侵蚀过程来实现闸门开口的优越的横截面形状。 因此，当执行拐角舍入处理顺序时，占位符材料的剩余部分可以有效地保护诸如高k电介质材料的底层敏感材料。
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5.发明申请公开(公告)号：US20080081403A1
公开(公告)日：2008-04-03
申请号：US11740072
申请日：2007-04-25
IPC分类号： H01L21/337
CPC分类号： H01L29/045 , H01L21/26506 , H01L21/26513 , H01L21/268 , H01L29/665 , H01L29/6659 , H01L29/7843
摘要： By appropriately adapting the length direction and width directions of transistor devices with respect to the crystallographic orientation of the semiconductor material such that identical vertical and horizontal growth planes upon re-crystallizing amorphized portions are obtained, the number of corresponding stacking faults may be significantly reduced. Hence, transistor elements with extremely shallow PN junctions may be formed on the basis of pre-amorphization implantation processes while substantially avoiding any undue side effects typically obtained in conventional techniques due to stacking faults.
摘要翻译： 通过适当地适应晶体管器件的长度方向和宽度方向相对于半导体材料的晶体取向，使得在重新结晶非晶化部分时相同的垂直和水平生长面，可以显着地减少对应的堆垛层错的数量。 因此，具有非常浅的PN结的晶体管元件可以基于前非晶化注入工艺形成，同时基本上避免了由于堆垛层错而在常规技术中通常获得的任何不适当的副作用。
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6.发明授权Method for reducing crystal defects in transistors with re-grown shallow junctions by appropriately selecting crystalline orientations 有权通过适当选择晶体取向，通过再生长的浅结减少晶体管晶体缺陷的方法公开(公告)号：US07763505B2
公开(公告)日：2010-07-27
申请号：US11740072
申请日：2007-04-25
IPC分类号： H01L21/337
CPC分类号： H01L29/045 , H01L21/26506 , H01L21/26513 , H01L21/268 , H01L29/665 , H01L29/6659 , H01L29/7843
摘要： By appropriately adapting the length direction and width directions of transistor devices with respect to the crystallographic orientation of the semiconductor material such that identical vertical and horizontal growth planes upon re-crystallizing amorphized portions are obtained, the number of corresponding stacking faults may be significantly reduced. Hence, transistor elements with extremely shallow PN junctions may be formed on the basis of pre-amorphization implantation processes while substantially avoiding any undue side effects typically obtained in conventional techniques due to stacking faults.
摘要翻译： 通过适当地适应晶体管器件的长度方向和宽度方向相对于半导体材料的晶体取向，使得在重新结晶非晶化部分时相同的垂直和水平生长面，可以显着地减少对应的堆垛层错的数量。 因此，具有非常浅的PN结的晶体管元件可以基于前非晶化注入工艺形成，同时基本上避免了由于堆垛层错而在常规技术中通常获得的任何不适当的副作用。
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7.发明申请TECHNIQUE FOR ENHANCING STRESS TRANSFER INTO CHANNEL REGIONS OF NMOS AND PMOS TRANSISTORS 有权用于增强NMOS和PMOS晶体管通道区域应力传递的技术公开(公告)号：US20070122966A1
公开(公告)日：2007-05-31
申请号：US11468450
申请日：2006-08-30
申请人： Jan Hoentschel , Andy Wei , Markus Lenski , Peter Javorka
发明人： Jan Hoentschel , Andy Wei , Markus Lenski , Peter Javorka
IPC分类号： H01L21/8238 , H01L21/44
CPC分类号： H01L21/823864 , H01L21/823807 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/7843
摘要： A method and a semiconductor device are provided in which respective contact layers having a specific intrinsic stress may be directly formed on respective metal silicide regions without undue metal silicide degradation during an etch process for removing an unwanted portion of an initially deposited contact layer. Moreover, due to the inventive concept, the strain-inducing contact layers may be formed directly on the respective substantially L-shaped spacer elements, thereby enhancing even more the stress transfer mechanism.
摘要翻译： 提供了一种方法和半导体器件，其中具有特定固有应力的各个接触层可以直接形成在各自的金属硅化物区域上，而在用于去除最初沉积的接触层的不希望的部分的蚀刻工艺期间不会有不适当的金属硅化物降解。 此外，由于本发明构思，应变感应接触层可以直接形成在相应的大致L形间隔元件上，从而进一步增强应力传递机构。
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8.发明授权Method for forming CMOS transistors having metal-containing gate electrodes formed on a high-K gate dielectric material 有权用于形成具有形成在高K栅极电介质材料上的含金属栅电极的CMOS晶体管的方法公开(公告)号：US08367495B2
公开(公告)日：2013-02-05
申请号：US12749112
申请日：2010-03-29
申请人： Sven Beyer , Markus Lenski , Richard Carter , Klaus Hempel
发明人： Sven Beyer , Markus Lenski , Richard Carter , Klaus Hempel
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842 , H01L21/28088 , H01L21/84 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/7833
摘要： During the formation of sophisticated gate electrode structures, a replacement gate approach may be applied in which plasma assisted etch processes may be avoided. To this end, one of the gate electrode structures may receive an intermediate etch stop liner, which may allow the replacement of the placeholder material and the adjustment of the work function in a later manufacturing stage. The intermediate etch stop liner may not negatively affect the gate patterning sequence.
摘要翻译： 在复杂的栅电极结构的形成期间，可以应用替代栅极方法，其中可以避免等离子体辅助蚀刻工艺。 为此，栅极电极结构之一可以接收中间蚀刻停止衬垫，其可以允许在稍后的制造阶段更换占位符材料和调整功能。 中间蚀刻停止衬垫可能不会对栅极图案化顺序产生负面影响。
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9.发明申请Maintaining Integrity of a High-K Gate Stack After Embedding a Stressor Material by Using a Liner 审中-公开通过使用衬垫嵌入应力材料后，保持高K栅极堆叠的完整性公开(公告)号：US20110266625A1
公开(公告)日：2011-11-03
申请号：US12963253
申请日：2010-12-08
申请人： Richard Carter , Sven Beyer , Markus Lenski , Patrick Press
发明人： Richard Carter , Sven Beyer , Markus Lenski , Patrick Press
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/6656 , H01L21/28247 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L21/84 , H01L29/165 , H01L29/4966 , H01L29/517 , H01L29/665 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： Gate failures in sophisticated high-k metal gate electrode structures formed in an early manufacturing stage may be reduced by forming a protective liner material after the incorporation of a strain-inducing semiconductor alloy and prior to performing any critical wet chemical processes. In this manner, attacks in the sensitive gate materials after the incorporation of the strain-inducing semiconductor material may be avoided, without influencing the further processing of the device. In this manner, very sophisticated circuit designs may be applied in sophisticated gate first approaches.
摘要翻译： 在早期制造阶段形成的复杂的高k金属栅电极结构中的栅极故障可以通过在引入应变诱导半导体合金之后并且在执行任何关键的湿化学工艺之前形成保护性衬垫材料来减少。 以这种方式，可以避免在引入应变诱导半导体材料之后在敏感栅极材料中的攻击，而不影响器件的进一步处理。 以这种方式，非常复杂的电路设计可以应用于复杂的门第一方法。
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10.发明申请公开(公告)号：US20100244141A1
公开(公告)日：2010-09-30
申请号：US12749112
申请日：2010-03-29
申请人： Sven Beyer , Markus Lenski , Richard Carter , Klaus Hempel
发明人： Sven Beyer , Markus Lenski , Richard Carter , Klaus Hempel
IPC分类号： H01L27/092 , H01L21/8234 , H01L21/28
CPC分类号： H01L21/823842 , H01L21/28088 , H01L21/84 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/7833
摘要： During the formation of sophisticated gate electrode structures, a replacement gate approach may be applied in which plasma assisted etch processes may be avoided. To this end, one of the gate electrode structures may receive an intermediate etch stop liner, which may allow the replacement of the placeholder material and the adjustment of the work function in a later manufacturing stage. The intermediate etch stop liner may not negatively affect the gate patterning sequence.
摘要翻译： 在复杂的栅电极结构的形成期间，可以应用替代栅极方法，其中可以避免等离子体辅助蚀刻工艺。 为此，栅极电极结构之一可以接收中间蚀刻停止衬垫，其可以允许在稍后的制造阶段更换占位符材料和调整功能。 中间蚀刻停止衬垫可能不会对栅极图案化顺序产生负面影响。
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