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公开(公告)号：US11502126B2
公开(公告)日：2022-11-15
申请号：US17097485
申请日：2020-11-13
IPC分类号： H01L27/22 , H01L21/768 , H01L43/12
摘要： A method for fabricating an integrated circuit is provided. The method includes depositing an etch stop layer over an interconnect layer having a conductive feature; depositing a protective layer over the etch stop layer; depositing a first dielectric layer over the protective layer; etching a via opening in the first dielectric layer, wherein the protective layer has a higher etch resistance to etching the via opening than that of the first dielectric layer; etching a portion of the protective layer exposed by the via opening; etching a portion of the etch stop layer exposed by the via opening, such that the via opening exposes the conductive feature; forming a bottom electrode via in the via opening; and forming a memory stack over the bottom electrode via.
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公开(公告)号：US11469269B2
公开(公告)日：2022-10-11
申请号：US16930499
申请日：2020-07-16
IPC分类号： H01L27/22 , H01L43/02 , H01F10/32 , H01L23/522 , H01L23/528 , H01L21/768 , H01L43/12 , H01F41/32 , H01L23/532
摘要： Some embodiments relate to an integrated chip. The integrated chip includes a first memory cell overlying a substrate and a second memory cell overlying the substrate. A dielectric structure overlies the substrate. A trench extends into the dielectric structure and is spaced laterally between the first memory cell and the second memory cell. A dielectric layer is disposed within the trench.
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公开(公告)号：US20210028350A1
公开(公告)日：2021-01-28
申请号：US17009905
申请日：2020-09-02
发明人： Ming-Che Ku , Harry-Hak-Lay Chuang , Hung Cho Wang , Tsun Chung Tu , Jiunyu Tsai , Sheng-Huang Huang
IPC分类号： H01L43/02 , H01F10/32 , H01L27/22 , H01L43/12 , H01L23/528 , H01L21/768 , H01F41/34 , H01L23/522
摘要： The present disclosure relates to a method of forming an integrated chip. The method includes forming an ILD layer over a memory device over a substrate. A hard mask structure is formed over the ILD layer and a patterning structure is formed over the hard mask structure. The hard mask structure has sidewalls defining a first opening directly over the memory device and centered along a first line perpendicular to an upper surface of the substrate. The patterning structure has sidewalls defining a second opening directly over the memory device and centered along a second line parallel to the first line. The second line is laterally offset from the first line by a non-zero distance. The ILD layer is etched below an overlap of the first and second openings to define a top electrode via hole. The top electrode via hole is with a conductive material.
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公开(公告)号：US20200350366A1
公开(公告)日：2020-11-05
申请号：US16930499
申请日：2020-07-16
IPC分类号： H01L27/22 , H01L43/02 , H01F10/32 , H01L23/522 , H01L23/528 , H01L21/768 , H01L43/12 , H01F41/32 , H01L23/532
摘要： Some embodiments relate to an integrated chip. The integrated chip includes a first memory cell overlying a substrate and a second memory cell overlying the substrate. A dielectric structure overlies the substrate. A trench extends into the dielectric structure and is spaced laterally between the first memory cell and the second memory cell. A dielectric layer is disposed within the trench.
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公开(公告)号：US10797230B2
公开(公告)日：2020-10-06
申请号：US16580419
申请日：2019-09-24
摘要： Some embodiments relate to a method for manufacturing a magnetoresistive random-access memory (MRAM) cell. The method includes forming a spacer layer surrounding at least a magnetic tunnel junction (MTJ) layer and a top electrode of the MRAM cell; etching the spacer layer to expose a top surface of the top electrode and a top surface of a spacer formed by the spacer layer; forming an upper etch stop layer over the top electrode top surface and the spacer top surface; and forming an upper metal layer in contact with the top electrode top surface of the MRAM cell. A width of the upper etch stop layer is greater than a width of a bottom surface of the upper metal layer.
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公开(公告)号：US11489107B2
公开(公告)日：2022-11-01
申请号：US17009905
申请日：2020-09-02
发明人： Ming-Che Ku , Harry-Hak-Lay Chuang , Hung Cho Wang , Tsun Chung Tu , Jiunyu Tsai , Sheng-Huang Huang
IPC分类号： H01L43/02 , H01F10/32 , H01L27/22 , H01L43/12 , H01L23/528 , H01L21/768 , H01F41/34 , H01L23/522 , G11C11/16
摘要： The present disclosure relates to a method of forming an integrated chip. The method includes forming an ILD layer over a memory device over a substrate. A hard mask structure is formed over the ILD layer and a patterning structure is formed over the hard mask structure. The hard mask structure has sidewalls defining a first opening directly over the memory device and centered along a first line perpendicular to an upper surface of the substrate. The patterning structure has sidewalls defining a second opening directly over the memory device and centered along a second line parallel to the first line. The second line is laterally offset from the first line by a non-zero distance. The ILD layer is etched below an overlap of the first and second openings to define a top electrode via hole. The top electrode via hole is with a conductive material.
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公开(公告)号：US11189659B2
公开(公告)日：2021-11-30
申请号：US16423276
申请日：2019-05-28
摘要： Some embodiments relate to an integrated circuit including a magnetoresistive random-access memory (MRAM) cell. The integrated circuit includes a semiconductor substrate and an interconnect structure disposed over the semiconductor substrate. The interconnect structure includes metal layers that are stacked over one another with dielectric layers disposed between. The metal layers include a lower metal layer and an upper metal layer disposed over the lower metal layer. A bottom electrode is disposed over and in electrical contact with the lower metal layer. A magnetic tunneling junction (MTJ) is disposed over an upper surface of bottom electrode. A top electrode is disposed over an upper surface of the MTJ. A sidewall spacer surrounds an outer periphery of the top electrode. Less than an entirety of a top electrode surface is in direct electrical contact with a metal via connected to the upper metal layer.
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公开(公告)号：US11075335B2
公开(公告)日：2021-07-27
申请号：US16408815
申请日：2019-05-10
发明人： Harry-Hak-Lay Chuang , Chen-Pin Hsu , Hung Cho Wang , Wen-Chun You , Sheng-Chang Chen , Tsun Chung Tu , Jiunyu Tsai , Sheng-Huang Huang
IPC分类号： H01L21/768 , H01L43/12 , H01L43/02 , H01F10/32 , H01L27/22 , H01L23/528 , H01F41/32 , H01L23/522
摘要： Some embodiments relate to a method for manufacturing a memory device. The method includes forming a first masking layer disposed over a dielectric layer, the first masking layer exhibiting sidewalls defining an opening disposed above a magnetoresistive random-access memory (MRAM) cell located in an embedded memory region. A first etch is performed to form a first via opening within the dielectric layer above the MRAM cell. A top electrode via layer formed over the MRAM cell and the dielectric layer. A first planarization process performed on the top electrode via layer to remove part of the top electrode via layer and define a top electrode via having a substantially flat top surface.
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公开(公告)号：US20210134668A1
公开(公告)日：2021-05-06
申请号：US17007260
申请日：2020-08-31
IPC分类号： H01L21/768 , G11C5/06 , G11C11/16 , H01L21/3213
摘要： The present disclosure relates to a method of forming an integrated chip. The method includes forming a memory device over a substrate and forming an etch stop layer over the memory device. An inter-level dielectric (ILD) layer is formed over the etch stop layer and laterally surrounding the memory device. One or more patterning process are performed to define a first trench extending from a top of the ILD layer to expose an upper surface of the etch stop layer. A removal process is performed to remove an exposed part of the etch stop layer. A conductive material is formed within the interconnect trench after performing the removal process.
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公开(公告)号：US10727274B2
公开(公告)日：2020-07-28
申请号：US16412714
申请日：2019-05-15
IPC分类号： H01L27/22 , H01L43/10 , H01L23/52 , H01L21/768 , H01L23/532 , H01L43/02 , H01F10/32 , H01L23/522 , H01L23/528 , H01L43/12 , H01F41/32
摘要： Some embodiments relate to a memory device. The memory device includes a first magnetoresistive random-access memory (MRAM) cell disposed on a substrate, and a second MRAM cell disposed on the substrate. An inter-level dielectric (ILD) layer is disposed over the substrate. The ILD layer comprises sidewalls defining a trough between the first and second MRAM cells. A dielectric layer disposed over the ILD layer. The dielectric layer completely fills the trough.
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