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公开(公告)号：US20240147716A1
公开(公告)日：2024-05-02
申请号：US18404676
申请日：2024-01-04
发明人： Wei Cheng Wu , Harry-Hak-Lay Chuang
IPC分类号： H10B41/30 , H01L21/28 , H01L21/306 , H01L21/321 , H01L21/8234 , H01L27/105 , H01L29/66 , H10B41/49 , H10B43/00 , H10B43/30
CPC分类号： H10B41/30 , H01L21/30604 , H01L21/3212 , H01L21/823462 , H01L27/105 , H01L29/40114 , H01L29/66545 , H10B41/49 , H10B43/00 , H10B43/30 , H10B10/18
摘要： An embedded flash memory device includes a gate stack, which includes a bottom dielectric layer extending into a recess in a semiconductor substrate, and a charge storage layer over the bottom dielectric layer. The charge storage layer includes a portion in the recess. The gate stack further includes a top dielectric layer over the charge storage layer, and a metal gate over the top dielectric layer. Source and drain regions are in the semiconductor substrate, and are on opposite sides of the gate stack.
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公开(公告)号：US11672124B2
公开(公告)日：2023-06-06
申请号：US17184953
申请日：2021-02-25
发明人： Harry-Hak-Lay Chuang , Wei Cheng Wu , Ya-Chen Kao , Yi Hsien Lu
IPC分类号： H10B43/40 , H01L29/66 , H01L29/423 , H01L29/51 , H01L27/11573 , H01L21/8234 , H01L27/092 , H01L27/088
CPC分类号： H01L27/11573 , H01L21/823462 , H01L27/092 , H01L29/42344 , H01L29/513 , H01L29/517 , H01L29/665 , H01L29/6656 , H01L29/66545 , H01L27/088
摘要： The present disclosure relates to an integrated circuit that includes a semiconductor substrate having a periphery region and memory cell region separated by a boundary region. A pair of split gate flash memory cells are disposed on the memory cell region and include a first select gate and a first memory gate. A first gate electrode is disposed over a first gate dielectric layer on the periphery region. A second gate electrode is disposed over a second gate dielectric layer on the periphery region at a position between the boundary region and the first gate electrode. The second dielectric layer is thicker than the first gate dielectric layer. The first select gate and the first memory gate have upper surfaces that are co-planar or level with the upper surface of the second gate electrode.
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3.发明授权公开(公告)号：US11659775B2
公开(公告)日：2023-05-23
申请号：US17342464
申请日：2021-06-08
摘要： An integrated circuit die includes a magnetic tunnel junction as a storage element of a MRAM cell. The integrated circuit die includes a top electrode positioned on the magnetic tunnel junction. The integrated circuit die includes a first sidewall spacer laterally surrounding the top electrode. The first sidewall spacer acts as a mask for patterning the magnetic tunnel junction. The integrated circuit die includes a second sidewalls spacer positioned on a lateral surface of the magnetic tunnel junction.
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公开(公告)号：US11506706B2
公开(公告)日：2022-11-22
申请号：US17126222
申请日：2020-12-18
发明人： Harry-Hak-Lay Chuang , Chih-Yang Chang , Ching-Huang Wang , Tien-Wei Chiang , Meng-Chun Shih , Chia Yu Wang
摘要： In some embodiments, a semiconductor wafer testing system is provided. The semiconductor wafer testing system includes a semiconductor wafer prober having one or more conductive probes, where the semiconductor wafer prober is configured to position the one or more conductive probes on an integrated chip (IC) that is disposed on a semiconductor wafer. The semiconductor wafer testing system also includes a ferromagnetic wafer chuck, where the ferromagnetic wafer chuck is configured to hold the semiconductor wafer while the wafer prober positions the one or more conductive probes on the IC. An upper magnet is disposed over the ferromagnetic wafer chuck, where the upper magnet is configured to generate an external magnetic field between the upper magnet and the ferromagnetic wafer chuck, and where the ferromagnetic wafer chuck amplifies the external magnetic field such that the external magnetic field passes through the IC with an amplified magnetic field strength.
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公开(公告)号：US11502126B2
公开(公告)日：2022-11-15
申请号：US17097485
申请日：2020-11-13
IPC分类号： H01L27/22 , H01L21/768 , H01L43/12
摘要： A method for fabricating an integrated circuit is provided. The method includes depositing an etch stop layer over an interconnect layer having a conductive feature; depositing a protective layer over the etch stop layer; depositing a first dielectric layer over the protective layer; etching a via opening in the first dielectric layer, wherein the protective layer has a higher etch resistance to etching the via opening than that of the first dielectric layer; etching a portion of the protective layer exposed by the via opening; etching a portion of the etch stop layer exposed by the via opening, such that the via opening exposes the conductive feature; forming a bottom electrode via in the via opening; and forming a memory stack over the bottom electrode via.
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公开(公告)号：US11469269B2
公开(公告)日：2022-10-11
申请号：US16930499
申请日：2020-07-16
IPC分类号： H01L27/22 , H01L43/02 , H01F10/32 , H01L23/522 , H01L23/528 , H01L21/768 , H01L43/12 , H01F41/32 , H01L23/532
摘要： Some embodiments relate to an integrated chip. The integrated chip includes a first memory cell overlying a substrate and a second memory cell overlying the substrate. A dielectric structure overlies the substrate. A trench extends into the dielectric structure and is spaced laterally between the first memory cell and the second memory cell. A dielectric layer is disposed within the trench.
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公开(公告)号：US11387114B2
公开(公告)日：2022-07-12
申请号：US16796667
申请日：2020-02-20
IPC分类号： H01L21/321 , H01L21/8234 , H01L29/78 , H01L29/49 , H01L29/66 , H01L27/088
摘要： A semiconductor device includes a substrate, a first well, a second well, a metal gate, a poly gate, a source region, and a drain region. The first well and the second well are within the substrate. The metal gate is partially over the first well. The poly gate is over the second well. The poly gate is separated from the metal gate, and a width ratio of the poly gate to the metal gate is in a range from about 0.1 to about 0.2. The source region and the drain region are respectively within the first well and the second well.
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公开(公告)号：US20210280773A1
公开(公告)日：2021-09-09
申请号：US17319590
申请日：2021-05-13
摘要： A memory cell with dual sidewall spacers and its manufacturing methods are provided. In some embodiments, the memory cell includes a bottom electrode disposed over a substrate, a resistance switching dielectric disposed over the bottom electrode and having a variable resistance, and a top electrode disposed over the resistance switching dielectric. The memory cell further includes a first sidewall spacer disposed on an upper surface of the bottom electrode and extending upwardly alongside the resistance switching dielectric and the top electrode. The memory cell further includes a second sidewall spacer having a bottom surface disposed on the upper surface of the bottom electrode and directly and conformally lining the first sidewall spacer.
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9.发明授权公开(公告)号：US11088083B2
公开(公告)日：2021-08-10
申请号：US16381410
申请日：2019-04-11
IPC分类号： H01L27/22 , H01L23/552 , H01L43/02 , H01L43/12 , H01L23/495 , H01L23/00
摘要： In some embodiments, the present application provides a memory device. The memory device includes a chip that includes a magnetic random access memory (MRAM) cell. A magnetic-field-shielding structure at least partially surrounding the chip including a multilayer stack. The multilayer stack includes a magnetic layer and a dielectric layer. A first magnetic region is located inside an inner surface of the magnetic field shielding structure and a second magnetic region is located immediately outside an outer surface of the magnetic field shielding structure. A magnetic field in the first magnetic region is less than a magnetic field in the second magnetic region.
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公开(公告)号：US20210233921A1
公开(公告)日：2021-07-29
申请号：US17231204
申请日：2021-04-15
发明人： Wei Cheng Wu , Harry-Hak-Lay Chuang
IPC分类号： H01L27/11521 , H01L27/11568 , H01L27/11563 , H01L21/28 , H01L27/105 , H01L27/11546 , H01L21/8234 , H01L29/66 , H01L21/306 , H01L21/321
摘要： An embedded flash memory device includes a gate stack, which includes a bottom dielectric layer extending into a recess in a semiconductor substrate, and a charge storage layer over the bottom dielectric layer. The charge storage layer includes a portion in the recess. The gate stack further includes a top dielectric layer over the charge storage layer, and a metal gate over the top dielectric layer. Source and drain regions are in the semiconductor substrate, and are on opposite sides of the gate stack.
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