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公开(公告)号：US11967469B2
公开(公告)日：2024-04-23
申请号：US17330929
申请日：2021-05-26
Applicant: TDK CORPORATION
Inventor： Hajime Kuwajima , Takashi Ohtsuka , Takeshi Oohashi , Yuichiro Okuyama
Abstract: Disclosed herein is an electronic component that includes a substrate, a planarizing layer covering a surface of the substrate, a first conductive layer formed on the planarizing layer and having a lower electrode, a dielectric film made of a material different from that of the planarizing layer and covering the planarizing layer and first conductive layer, an upper electrode laminated on the lower electrode through the dielectric film, and a first insulating layer covering the first conductive layer, dielectric film, and upper electrode. An outer periphery of the first insulating layer directly contacts the planarizing layer without an intervention of the dielectric film.
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公开(公告)号：US20190313528A1
公开(公告)日：2019-10-10
申请号：US16374556
申请日：2019-04-03
Applicant: TDK Corporation
Inventor： Hajime Kuwajima , Tomonaga Nishikawa , Takashi Ohtsuka , Takeshi Oohashi , Yuichiro Okuyama , Manabu Yamatani
Abstract: Disclosed herein is a multilayer wiring structure that includes a first metal layer; an interlayer insulating film formed on the first metal layer, the interlayer insulating film having an opening that exposes a first area of the first metal layer; a second metal layer formed on an inner wall of the opening; and a third metal layer filling the opening via the second metal layer. The first and third metal layers are direct contact with each other at a bottom of the opening.
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公开(公告)号：US10426032B1
公开(公告)日：2019-09-24
申请号：US16374556
申请日：2019-04-03
Applicant: TDK Corporation
Inventor： Hajime Kuwajima , Tomonaga Nishikawa , Takashi Ohtsuka , Takeshi Oohashi , Yuichiro Okuyama , Manabu Yamatani
Abstract: Disclosed herein is a multilayer wiring structure that includes a first metal layer; an interlayer insulating film formed on the first metal layer, the interlayer insulating film having an opening that exposes a first area of the first metal layer; a second metal layer formed on an inner wall of the opening; and a third metal layer filling the opening via the second metal layer. The first and third metal layers are direct contact with each other at a bottom of the opening.
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Patent Agency Ranking
公开(公告)号：US11452209B2
公开(公告)日：2022-09-20
申请号：US17134316
申请日：2020-12-26
Applicant: TDK CORPORATION
Inventor： Yuichiro Okuyama , Takeshi Oohashi , Hajime Kuwajima , Takashi Ohtsuka , Kazuhiro Yoshikawa , Kenichi Yoshida
Abstract: Disclosed herein is an electronic component that includes a substrate and a plurality of conductive layers and a plurality of insulating layers which are alternately laminated on the substrate. The side surface of at least one of the plurality of insulating layers has a recessed part set back from a side surface of the substrate and a projecting part projecting from the recessed part.
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公开(公告)号：US10454440B2
公开(公告)日：2019-10-22
申请号：US15679928
申请日：2017-08-17
Applicant: TDK Corporation
Inventor： Takeshi Oohashi
Abstract: Disclosed herein is a directional coupler that includes a main line configured to transmit a high-frequency signal, a sub line electromagnetically coupled to the main line, and a ground pattern positioned at least partially between the main line and the sub line in a plan view. The sub line includes a low pass filter having an inductance pattern and a capacitor. The ground pattern has an opening that overlaps at least the inductance pattern in a plan view.
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公开(公告)号：US09531053B2
公开(公告)日：2016-12-27
申请号：US15049834
申请日：2016-02-22
Applicant: TDK Corporation
Inventor： Toshiyasu Fujiwara , Chengbin Lin , Takeshi Oohashi , Yukio Mitake
Abstract: A directional coupler including a main line having an input terminal and an output terminal, and a sub-line having a coupling terminal and an isolation terminal, the main line, the sub-line, the input terminal, the output terminal, the coupling terminal and the isolation terminal being disposed within a laminate, wherein the main line and the sub-line extend in a loop shape in parallel with and spaced apart from each other by a gap such that electromagnetic coupling is generated therebetween and such that the main line is positioned outside the sub-line on a coupling layer, the input terminal, the output terminal, the coupling terminal and the isolation terminal are disposed outside the main line, and the main line is interposed between the output terminal and the sub-line.
Abstract translation: 一种定向耦合器，包括具有输入端和输出端的主线，以及具有耦合端子和隔离端子的子线，主线，子线，输入端，输出端，耦合端 并且所述隔离端子设置在层压体内，其中所述主线路和所述子线路以与所述主线路和所述子线路之间的间隔彼此平行并间隔开的环形延伸，使得在其间产生电磁耦合，并且所述主线路 位于耦合层的子线外侧，输入端子，输出端子，耦合端子和隔离端子配置在主线的外侧，主线插在输出端子与副线之间。
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公开(公告)号：US11545303B2
公开(公告)日：2023-01-03
申请号：US17143581
申请日：2021-01-07
Applicant: TDK CORPORATION
Inventor： Kazuhiro Yoshikawa , Kenichi Yoshida , Takashi Ohtsuka , Yuichiro Okuyama , Takeshi Oohashi , Hajime Kuwajima
Abstract: Disclosed herein is an electronic component that includes a substrate; and a plurality of conductive layers and a plurality of insulating layers which are alternately laminated on the substrate. The side surface of a predetermined one of the plurality of insulating layers has a recessed part set back from a side surface of the substrate and a projecting part projecting from the recessed part. The recessed part is covered with a first dielectric film made of an inorganic insulating material.
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公开(公告)号：US11357110B2
公开(公告)日：2022-06-07
申请号：US17132626
申请日：2020-12-23
Applicant: TDK Corporation
Inventor： Takeshi Oohashi , Shinichiro Toda , Daiki Kusunoki , Takashi Ohtsuka , Kazuhiro Yoshikawa , Kenichi Yoshida
Abstract: Disclosed herein is an electronic component that includes a first conductive layer including a lower electrode and a first inductor pattern, a dielectric film that covers the lower electrode, an upper electrode laminated on the lower electrode through the dielectric film, an insulating layer that covers the first conductive layer, dielectric film, and upper electrode, and a second conductive layer formed on the insulating layer and including a second inductor pattern. The first and second inductor patterns are connected in parallel through via conductors penetrating the insulating layer.
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