公开(公告)号：US20200252073A1

公开(公告)日：2020-08-06

申请号：US16854077

申请日：2020-04-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Atul Kumar AGRAWAL ,  Gautam Salil NANDI ,  Siddharth MALHOTRA ,  Tanmay NEEMA

IPC: H03M1/10

Abstract: An integrated circuit includes a digital-to-analog converter (DAC) core including a plurality of thermometric arms and an R-2R ladder, the DAC core to convert a DAC code to an analog signal. The integrated circuit includes additional components as well. A differential non-linearity (DNL) calibration circuit outputs DNL coefficients based on the DAC code. A memory stores a value indicative of a product of a resistor temperature coefficient (TC) and a resistor self-heating coefficient (SHC). A current DAC (IDAC) couples to the R-2R ladder. A self-heating calibration circuit generates a self-heating trim code based on the value from the memory. An adder adds a value indicative of the DNL coefficients with the self-heating trim code to generate an IDAC trim code and provides the IDAC trim code to the IDAC to trim the R-2R ladder.

公开(公告)号：US20210194479A1

公开(公告)日：2021-06-24

申请号：US17194474

申请日：2021-03-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rishubh KHURANA ,  Tanmay NEEMA ,  Kanak Chandra DAS ,  Atul Kumar AGRAWAL

IPC: H03K17/22 ,  H03K17/30 ,  G06F1/24

Abstract: An integrated circuit includes a power-on reset (POR) circuit and a digital logic circuit. The POR has first and second control outputs. The POR circuit is configured to generate a first control signal on the first control output responsive to a supply voltage on the supply voltage node exceeding a first threshold voltage and is configured to generate a second control signal on the second control output responsive to the supply voltage exceeding a second threshold voltage. The digital logic circuit has a first control input coupled to the first control output of the POR circuit and has a second control input coupled to the second control output of the POR circuit. The digital logic circuit is configured to initiate a first read transaction responsive to assertion of the first control signal and to initiate a second read transaction responsive to assertion of the second control signal.

公开(公告)号：US20200162090A1

公开(公告)日：2020-05-21

申请号：US16197132

申请日：2018-11-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Atul Kumar AGRAWAL ,  Gautam Salil NANDI ,  Siddharth MALHOTRA ,  Tanmay NEEMA

IPC: H03M1/10

Abstract: An integrated circuit includes a digital-to-analog converter (DAC) core including a plurality of thermometric arms and an R-2R ladder, the DAC core to convert a DAC code to an analog signal. The integrated circuit includes additional components as well. A differential non-linearity (DNL) calibration circuit outputs DNL coefficients based on the DAC code. A memory stores a value indicative of a product of a resistor temperature coefficient (TC) and a resistor self-heating coefficient (SHC). A current DAC (IDAC) couples to the R-2R ladder. A self-heating calibration circuit generates a self-heating trim code based on the value from the memory. An adder adds a value indicative of the DNL coefficients with the self-heating trim code to generate an IDAC trim code and provides the IDAC trim code to the IDAC to trim the R-2R ladder.

公开(公告)号：US20240178838A1

公开(公告)日：2024-05-30

申请号：US18058988

申请日：2022-11-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Atul Kumar AGRAWAL ,  Abhijit Patki ,  Shaik BASHA

IPC: H03K19/00 ,  G06F3/16 ,  H03K5/01 ,  H03K19/21 ,  H04R3/00 ,  H04R3/12

CPC classification number: H03K19/0002 ,  G06F3/162 ,  H03K5/01 ,  H03K19/21 ,  H04R3/005 ,  H04R3/12 ,  H03K2005/00013

Abstract: An integrated circuit (IC) includes a tristatable output buffer having a control input. The IC includes an input buffer having a buffer output. The IC further includes a delay circuit having a delay circuit input, a first delay circuit output, and a second delay circuit output. The delay circuit input is coupled to the buffer output. The IC also includes a tristate circuit coupled to the first delay circuit output and to the second delay circuit output. The tristate circuit having a tristate circuit output coupled to the control input.

公开(公告)号：US20210036701A1

公开(公告)日：2021-02-04

申请号：US16880541

申请日：2020-05-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rishubh KHURANA ,  Tanmay NEEMA ,  Kanak Chandra DAS ,  Atul Kumar AGRAWAL

IPC: H03K17/22 ,  H03K17/30 ,  H03K17/14 ,  G06F1/24 ,  G11C11/4099 ,  G11C11/4074

Abstract: An integrated circuit includes a power-on reset (POR) circuit and a digital logic circuit. The POR has first and second control outputs. The POR circuit is configured to generate a first control signal on the first control output responsive to a supply voltage on the supply voltage node exceeding a first threshold voltage and is configured to generate a second control signal on the second control output responsive to the supply voltage exceeding a second threshold voltage. The digital logic circuit has a first control input coupled to the first control output of the POR circuit and has a second control input coupled to the second control output of the POR circuit. The digital logic circuit is configured to initiate a first read transaction responsive to assertion of the first control signal and to initiate a second read transaction responsive to assertion of the second control signal.