公开(公告)号：US20220319627A1

公开(公告)日：2022-10-06

申请号：US17843897

申请日：2022-06-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Devanathan VARADARAJAN ,  Varun SINGH

IPC: G11C29/44 ,  G11C29/42 ,  G11C29/14 ,  G11C17/16

Abstract: A system includes a processor and a memory set coupled to the processor. The system also includes a repair circuit coupled to the memory set. The repair circuit includes a first repair circuit and a second repair circuit. The repair circuit also includes a test controller configured to select between the first repair circuit and the second repair circuit to perform an in-field self-repair of the memory set.

公开(公告)号：US20230146764A1

公开(公告)日：2023-05-11

申请号：US18148312

申请日：2022-12-29

Applicant: Texas Instruments Incorporated

Inventor： Francisco Adolfo CANO ,  Devanathan VARADARAJAN ,  Anthony Martin HILL

IPC: G11C29/38 ,  G11C29/50 ,  G11C11/419 ,  G11C11/418 ,  G11C11/412

CPC classification number: G11C29/38 ,  G11C29/50004 ,  G11C11/419 ,  G11C11/418 ,  G11C11/412 ,  G11C2029/5004

Abstract: Systems of screening memory cells of a memory include modulating bitline and/or wordline voltage. In a read operation, the wordline may be overdriven or underdriven with respect to a nominal operating voltage on the wordline. In a write operation, one or both of the bitline and wordline may be overdriven or underdriven with respect to corresponding a nominal operating voltage. Such a system has margin control circuity, which may be in the form of bitline and wordline margin controls, to modulate bitline and wordline voltages, respectively, in the memory cells of the memory array.

公开(公告)号：US20230185633A1

公开(公告)日：2023-06-15

申请号：US17551011

申请日：2021-12-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Devanathan VARADARAJAN ,  Varun SINGH ,  Jose Luis FLORES ,  Rejitha NAIR ,  David Matthew THOMPSON

IPC: G06F9/50 ,  G06F11/30 ,  G06F11/32

CPC classification number: G06F9/5094 ,  G06F9/5016 ,  G06F11/3086 ,  G06F11/321

Abstract: An integrated circuit comprises a set of processor cores, wherein each processor core of the set of processor cores includes BIST logic circuitry and multiple memory blocks coupled to the BIST logic circuitry. Each processor core further includes multiple power control circuitry, where each power control circuitry of the multiple power control circuitry is coupled to a respective processor core of the set of processor cores, multiple isolation circuitry, where each isolation circuitry of the multiple isolation circuitry is coupled to a respective processor core of the set of processor cores, a built-in-self repair (BISR) controller coupled to the each of the set of processor cores, each of the multiple power control circuitry, and each of the multiple isolation circuitry, and a safety controller coupled to the BISR controller, the multiple power control circuitry, and to the multiple isolation circuitry.

公开(公告)号：US20200321071A1

公开(公告)日：2020-10-08

申请号：US16539805

申请日：2019-08-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Devanathan VARADARAJAN ,  Varun SINGH

IPC: G11C29/44 ,  G11C29/14 ,  G11C29/42 ,  G11C17/16

Abstract: A system includes a processor and a memory set coupled to the processor. The system also includes a repair circuit coupled to the memory set. The repair circuit includes a first repair circuit and a second repair circuit. The repair circuit also includes a test controller configured to select between the first repair circuit and the second repair circuit to perform an in-field self-repair of the memory set.

公开(公告)号：US20250123903A1

公开(公告)日：2025-04-17

申请号：US18999134

申请日：2024-12-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Devanathan VARADARAJAN ,  Varun SINGH ,  Jose Luis FLORES ,  Rejitha NAIR ,  David Matthew THOMPSON

IPC: G06F9/50 ,  G06F11/30 ,  G06F11/32

Abstract: An example circuit, e.g., an integrated circuit, comprises processor cores, each of which includes multiple memory blocks; power control circuits respectively coupled to the processor cores; isolation circuits respectively coupled to the processor cores; and controller circuitry coupled to each of the processor cores, to each of the power control circuits, and to each of the isolation circuits. The controller circuitry is configured to select a subset of processor cores of the processor cores and a subset of memory blocks of the subset of processor cores for testing; and cause non-selected memory blocks of the processor cores to be at least one of power gated, clock gated, and isolated from the selected subset of memory blocks.

公开(公告)号：US20240321378A1

公开(公告)日：2024-09-26

申请号：US18736779

申请日：2024-06-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Devanathan VARADARAJAN ,  Varun SINGH

IPC: G11C29/44 ,  G11C29/16 ,  G11C29/40

CPC classification number: G11C29/4401 ,  G11C29/16 ,  G11C29/40

Abstract: Circuits and methods are directed to repairable memory systems and memory repair processes. An example circuit includes first and second logic coupled together. The first logic receives a plurality of instances of defect data from a plurality of memories, respectively, in which each of the plurality of instances of defect data has a memory-specific format. The first logic converts each of the plurality of instances of defect data to a common format and merges the plurality instances of defect data in the common format to generate merged data. The second logic receives the merged data and determines a plurality of instances of repair data for the plurality of instances of defect data, respectively, based on the merged data.

公开(公告)号：US20230253062A1

公开(公告)日：2023-08-10

申请号：US18301327

申请日：2023-04-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Devanathan VARADARAJAN ,  Varun SINGH

IPC: G11C29/44 ,  G11C29/16 ,  G11C29/40

CPC classification number: G11C29/4401 ,  G11C29/16 ,  G11C29/40

Abstract: In a described example, an integrated circuit (IC) includes a repairable memory system. A repair controller is coupled to the repairable memory system. The repair controller includes compression logic configured to encode memory repair code data for a respective instance of the repairable memory system and provide compressed repair data. A non-volatile memory controller is coupled to the repair controller and to non-volatile memory. The non-volatile memory controller is configured to transfer the compressed repair data to the non-volatile memory for storage.

公开(公告)号：US20200294614A1

公开(公告)日：2020-09-17

申请号：US16817096

申请日：2020-03-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Francisco Adolfo CANO ,  Devanathan VARADARAJAN ,  Anthony Martin HILL

IPC: G11C29/38 ,  G11C29/50 ,  G11C11/412 ,  G11C11/419 ,  G11C11/418

Abstract: Systems and methods of screening memory cells by modulating bitline and/or wordline voltage. In a read operation, the wordline may be overdriven or underdriven as compared to a nominal operating voltage on the wordline. In a write operation, the one or both of the bitline and wordline may be overdriven or underdriven as compared to a nominal operating voltage of each. A built-in self test (BIST) system for screening a memory array has bitline and wordline margin controls to modulate bitline and wordline voltage, respectively, in the memory array.