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    RESONANT RECTIFIER CIRCUIT WITH CAPACITOR SENSING
    1.
    发明申请
    RESONANT RECTIFIER CIRCUIT WITH CAPACITOR SENSING 审中-公开

    公开(公告)号：US20190386575A1

    公开(公告)日：2019-12-19

    申请号：US16554095

    申请日：2019-08-28

    Applicant: Texas Instruments Incorporated

    Inventor： Mustapha El Markhi ,  Erhan Ozalevli ,  Tuli Dake ,  Dingkun Du ,  Gianpaolo Lisi ,  Jingwei Xu

    IPC: H02M3/335

    Abstract: A wireless power transfer system using a resonant rectifier circuit with capacitor sensing. A wireless power transfer system includes a power receiver resonant circuit and a synchronous rectifier. The power receiver resonant circuit includes an inductor and a capacitor connected in series with the inductor. The synchronous rectifier is configured to identify zero crossings of alternating current flowing through the inductor based on voltage across the capacitor, and control synchronous rectification of the alternating current based on timing of the zero crossings.

    Synchronization circuit
    3.
    发明授权
    Synchronization circuit 有权
    同步电路

    公开(公告)号：US09292038B1

    公开(公告)日：2016-03-22

    申请号：US14531685

    申请日：2014-11-03

    Applicant: Texas Instruments Incorporated

    Inventor： Erhan Ozalevli

    IPC: G06F1/04 ,  G06F1/12

    CPC classification number: G06F1/12 ,  G06F1/263

    Abstract: A synchronization circuit receives an external clock input. The circuit includes an internal oscillator; a clock detection circuit, coupled to the external clock input, for determining whether a clock signal at the external clock input is valid; circuitry for keeping the frequency of the internal oscillator constant until the clock detection circuit determines that an external clock signal is valid; and circuitry for switching the output of the synchronization circuit from the internal oscillator to the external clock input when the clock detection circuit determines than an external clock signal is valid.

    Abstract translation: 同步电路接收外部时钟输入。 该电路包括一个内部振荡器; 时钟检测电路，耦合到所述外部时钟输入，用于确定所述外部时钟输入处的时钟信号是否有效; 用于保持内部振荡器的频率恒定的电路，直到时钟检测电路确定外部时钟信号有效; 以及当时钟检测电路确定而不是外部时钟信号时，用于将同步电路的输出从内部振荡器切换到外部时钟输入的电路是有效的。

    Phase-locked loop (PLL) circuit
    4.
    发明授权
    Phase-locked loop (PLL) circuit 有权

    公开(公告)号：US10200048B2

    公开(公告)日：2019-02-05

    申请号：US15346248

    申请日：2016-11-08

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Erhan Ozalevli ,  Mustapha El Markhi ,  Tuli Dake

    IPC: H03L7/06 ,  H03L7/099 ,  H03L7/085 ,  H03L7/113 ,  H03K3/0231

    Abstract: One example includes a phase-locked loop (PLL) circuit. The circuit includes a frequency divider and phase detector configured to generate a plurality of non-overlapping switching signals based on an input signal and a PLL output signal. The circuit also includes a linear frequency-to-current (F2I) converter configured to generate a control current having an amplitude that is based on the plurality of non-overlapping switching signals. The circuit further includes a linear current-controlled oscillator configured to generate the PLL output signal to have a frequency and phase to be approximately equal to the input signal based on the amplitude of the control current.

    Battery charging and measurement circuit
    5.
    发明授权
    Battery charging and measurement circuit 有权

    公开(公告)号：US11646594B2

    公开(公告)日：2023-05-09

    申请号：US17156909

    申请日：2021-01-25

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Mustapha El Markhi ,  Erhan Ozalevli ,  Tuli Dake ,  Rohit Bhan

    IPC: H02J7/00 ,  H02J7/14 ,  H03M1/66

    CPC classification number: H02J7/00714 ,  H03M1/66

    Abstract: An example device comprises a digital-to-analog converter (DAC) comprising first and second transistors coupled to a first amplifier, the second transistor coupled to a first output of the DAC and to an output of the first amplifier, and third and fourth transistors coupled to the first amplifier and to a second output of the DAC, the third and fourth transistors switchably coupled to a voltage supply and to the first transistor. The device also comprises a first node coupled to the first output of the DAC and to a resistor. The device further includes a second node coupled to the second output of the DAC, and a second amplifier coupled to the second node and to the first transistor and switchably coupled to the third and fourth transistors. The device also comprises a comparator coupled to the first node.

    Phase-locked loop (PLL) circuit
    7.
    发明授权
    Phase-locked loop (PLL) circuit 有权

    公开(公告)号：US11101807B2

    公开(公告)日：2021-08-24

    申请号：US16216162

    申请日：2018-12-11

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Erhan Ozalevli ,  Mustapha El Markhi ,  Tuli Dake

    IPC: H03L7/18 ,  H03L7/099 ,  H03L7/085 ,  H03L7/113 ,  H03K3/0231

    Abstract: One example includes a phase-locked loop (PLL) circuit. The circuit includes a frequency divider and phase detector configured to generate a plurality of non-overlapping switching signals based on an input signal and a PLL output signal. The circuit also includes a linear frequency-to-current (F2I) converter configured to generate a control current having an amplitude that is based on the plurality of non-overlapping switching signals. The circuit further includes a linear current-controlled oscillator configured to generate the PLL output signal to have a frequency and phase to be approximately equal to the input signal based on the amplitude of the control current.

    Battery charging and measurement circuit
    8.
    发明授权
    Battery charging and measurement circuit 有权

    公开(公告)号：US10938403B2

    公开(公告)日：2021-03-02

    申请号：US16191225

    申请日：2018-11-14

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Mustapha El Markhi ,  Erhan Ozalevli ,  Tuli Dake ,  Rohit Bhan

    IPC: H02J7/00 ,  H02J7/14 ,  H03M1/66

    Abstract: An example device comprises a digital-to-analog converter (DAC) comprising first and second transistors coupled to a first amplifier, the second transistor coupled to a first output of the DAC and to an output of the first amplifier, and third and fourth transistors coupled to the first amplifier and to a second output of the DAC, the third and fourth transistors switchably coupled to a voltage supply and to the first transistor. The device also comprises a first node coupled to the first output of the DAC and to a resistor. The device further includes a second node coupled to the second output of the DAC, and a second amplifier coupled to the second node and to the first transistor and switchably coupled to the third and fourth transistors. The device also comprises a comparator coupled to the first node.

    Signal reconstruction circuit
    9.
    发明授权
    Signal reconstruction circuit 有权

    公开(公告)号：US10469073B1

    公开(公告)日：2019-11-05

    申请号：US16047589

    申请日：2018-07-27

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Erhan Ozalevli ,  Mustapha El Markhi ,  Rohit Bhan

    IPC: H03K17/16 ,  H03K17/082 ,  H02M3/335

    Abstract: Aspects of the present disclosure provide for a circuit, comprising a first node configured to couple to a first current source and a second current source. The circuit also comprises a first filter configured to couple between a voltage supply and the first node, the first filter being a first dynamically controllable current filter. The circuit further comprises a current mirror coupled between the first node and a second node configured to couple to a third current source and a fourth current source. The circuit additionally comprises a second filter configured to couple between the second node and a ground node, the second filter being a second dynamically controllable current filter.

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