公开(公告)号：US20240113102A1

公开(公告)日：2024-04-04

申请号：US17957931

申请日：2022-09-30

Applicant: Texas Instruments Incorporated

Inventor： Umamaheswari Aghoram ,  Guruvayurappan Mathur ,  Robert Oppen ,  Tawen Mei

IPC: H01L27/06 ,  H01L29/66 ,  H01L29/94

CPC classification number: H01L27/0629 ,  H01L29/66181 ,  H01L29/945

Abstract: A microelectronic device includes a buried trench capacitor below an electronic component of the microelectronic device. In one embodiment, the buried trench capacitor may be formed between a silicon oxide capped p-type buried trench capacitor polysilicon region and a buried trench capacitor deep n-type region separated by buried trench capacitor liner dielectric. In a second embodiment, the buried trench capacitor may be formed by a buried trench capacitor polysilicon region and a p-type silicon epitaxial region separated by a buried trench capacitor liner dielectric. One terminal of the deep trench capacitor is made through the substrate via a deep trench substrate contact. The second terminal of the deep trench capacitor is made via a well contact that connects to the capacitor through a deep well region in one embodiment and through a polysilicon layer in a second embodiment.

公开(公告)号：US20240038580A1

公开(公告)日：2024-02-01

申请号：US17877976

申请日：2022-07-31

Applicant: Texas Instruments Incorporated

Inventor： Hao Yang ,  Asad Haider ,  Guruvayurappan Mathur ,  Abbas Ali ,  Alexei Sadovnikov ,  Umamaheswari Aghoram

IPC: H01L21/762 ,  H01L29/06

CPC classification number: H01L21/76229 ,  H01L29/0623

Abstract: An electronic device includes a semiconductor substrate and a semiconductor surface layer having a first conductivity type, the semiconductor surface layer over the semiconductor substrate and having a top surface, a buried layer having an opposite second conductivity type between the semiconductor surface layer and the semiconductor substrate, a dielectric isolation layer that extends over and into the semiconductor surface layer, a deep trench structure that extends through the dielectric isolation layer into the semiconductor surface layer, and a silicide blocking layer on a top surface of the deep trench structure.

公开(公告)号：US11239230B2

公开(公告)日：2022-02-01

申请号：US16665288

申请日：2019-10-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abbas Ali ,  Guruvayurappan Mathur ,  Poornika Fernandes

IPC: H01L27/07 ,  H01L27/06 ,  H01L49/02 ,  H01L29/06

Abstract: An integrated circuit (IC) includes a second metal level located between first and third metal levels, a dielectric layer located over the metal levels, and first, second and third vias within the dielectric layer. The first via traverses the first dielectric layer from a surface of the dielectric layer to the first metal level and has a first diameter. The second via traverses the dielectric layer from the surface to the second metal level and has the first diameter. The third via traverses the dielectric layer from the surface to the third metal level and has a second diameter greater than the first diameter. In some implementations the first, second and third metal levels implement a capacitor.

公开(公告)号：US20190181134A1

公开(公告)日：2019-06-13

申请号：US15838876

申请日：2017-12-12

Applicant: Texas Instruments Incorporated

Inventor： Akram Ali Salman ,  Guruvayurappan Mathur ,  Ryo Tsukahara

IPC: H01L27/02 ,  H01L29/73 ,  H01L29/08 ,  H01L27/06 ,  H01L29/66

CPC classification number: H01L27/0262 ,  H01L27/0259 ,  H01L27/0623 ,  H01L29/0646 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/66234 ,  H01L29/66287 ,  H01L29/7302 ,  H01L29/7304

Abstract: Disclosed examples provide fabrications methods and integrated circuits with back ballasted NPN bipolar transistors which include an n-type emitter in a P doped region, a p-type base with a first side facing the emitter, and an n-type collector laterally spaced from a second side of the base, where the collector includes a first side facing the second side of the base, an opposite second side, a silicided first collector portion and a silicide blocked second collector portion covered with a non-conductive dielectric that extends laterally between the first collector portion and the second side of the collector to provide back side ballasting for lateral breakdown and low current conduction via a deep N doped region while the vertical NPN turns on at a high voltage.

公开(公告)号：US11521961B2

公开(公告)日：2022-12-06

申请号：US16914579

申请日：2020-06-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Akram Ali Salman ,  Guruvayurappan Mathur ,  Ryo Tsukahara

IPC: H01L27/02 ,  H01L27/06 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/73

Abstract: An integrated circuit includes a bipolar transistor, e.g. a back-ballasted NPN, that can conduct laterally and vertically. At a low voltage breakdown and low current conduction occur laterally near a substrate surface, while at a higher voltage vertical conduction occurs in a more highly-doped channel below the surface. A relatively high-resistance region at the surface has a low doping level to guide the conduction deeper into the collector.

公开(公告)号：US11469315B2

公开(公告)日：2022-10-11

申请号：US17017341

申请日：2020-09-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Alexei Sadovnikov ,  Natalia Lavrovskaya ,  Guruvayurappan Mathur

IPC: H01L29/735 ,  H01L29/66 ,  H01L29/423

Abstract: In a described example, a bipolar junction transistor includes a substrate. An emitter region, a base region, and a collector region are each formed in the substrate. A gate-type structure is formed on the substrate between the base region and the emitter region. A contact is coupled to the gate-type structure, and the contact is adapted to be coupled to a source of DC voltage.

公开(公告)号：US20200350405A1

公开(公告)日：2020-11-05

申请号：US16931935

申请日：2020-07-17

Applicant: Texas Instruments Incorporated

Inventor： Chin-yu Tsai ,  Guruvayurappan Mathur

IPC: H01L29/10 ,  H01L21/8238 ,  H01L29/45 ,  H01L21/74 ,  H01L21/285 ,  H01L21/324 ,  H01L29/78 ,  H01L21/265 ,  H01L27/092 ,  H01L21/266 ,  H01L29/66 ,  H01L21/225

Abstract: An integrated circuit includes an extended drain MOS transistor. The substrate of the integrated circuit has a lower layer with a first conductivity type. A drain well of the extended drain MOS transistor has the first conductivity type. The drain well is separated from the lower layer by a drain isolation well having a second, opposite, conductivity type. A source region of the extended drain MOS transistor is separated from the lower layer by a body well having the second conductivity type. Both the drain isolation well and the body well contact the lower layer. An average dopant density of the second conductivity type in the drain isolation well is less than an average dopant density of the second conductivity type in the body well.

公开(公告)号：US20200328204A1

公开(公告)日：2020-10-15

申请号：US16914579

申请日：2020-06-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Akram Ali Salman ,  Guruvayurappan Mathur ,  Ryo Tsukahara

IPC: H01L27/02 ,  H01L29/73 ,  H01L29/66 ,  H01L27/06 ,  H01L29/08 ,  H01L29/06

Abstract: Disclosed examples provide fabrications methods and integrated circuits with back ballasted NPN bipolar transistors which include an n-type emitter in a P doped region, a p-type base with a first side facing the emitter, and an n-type collector laterally spaced from a second side of the base, where the collector includes a first side facing the second side of the base, an opposite second side, a silicided first collector portion and a silicide blocked second collector portion covered with a non-conductive dielectric that extends laterally between the first collector portion and the second side of the collector to provide back side ballasting for lateral breakdown and low current conduction via a deep N doped region while the vertical NPN turns on at a high voltage.

公开(公告)号：US20240038579A1

公开(公告)日：2024-02-01

申请号：US17877964

申请日：2022-07-31

Applicant: Texas Instruments Incorporated

Inventor： Asad Haider ,  Hao Yang ,  Guruvayurappan Mathur ,  Alexei Sadovnikov ,  Abbas Ali ,  Umamaheswari Aghoram

IPC: H01L21/762 ,  H01L29/06

CPC classification number: H01L21/76229 ,  H01L29/0623

Abstract: An electronic device includes a semiconductor substrate and a semiconductor surface layer having a first conductivity type, as well as a buried layer, a deep trench structure and a shallow trench isolation structure, the semiconductor surface layer over the semiconductor substrate and having a top surface, the buried layer having an opposite second conductivity type between the semiconductor surface layer and the semiconductor substrate, the deep trench structure including a trench that extends through the semiconductor surface layer and into the buried layer, a dielectric liner on a sidewall of the trench from the semiconductor surface layer to the buried layer, and polysilicon that extends on the dielectric liner and fills the trench to the side of the semiconductor surface layer, the shallow trench isolation structure extends into the semiconductor surface layer, and the shallow trench isolation structure in contact with the deep trench structure.

公开(公告)号：US20230253495A1

公开(公告)日：2023-08-10

申请号：US17665381

申请日：2022-02-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jingjing Chen ,  Ming-Yeh Chuang ,  Guruvayurappan Mathur ,  James Todd ,  Ronald Chin ,  Thomas Lillibridge

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/7825 ,  H01L29/4236 ,  H01L29/41758 ,  H01L29/66515

Abstract: The present disclosure generally relates to a bird's beak profile of a field oxide region. In an example, a semiconductor device structure includes a semiconductor substrate, a dielectric oxide layer, and a field oxide region. The semiconductor substrate has a top surface. The dielectric oxide layer is over the top surface of the semiconductor substrate. The field oxide region is over the semiconductor substrate. The field oxide region is connected to the dielectric oxide layer through a bird's beak region. A lower surface of the bird's beak region interfaces with the semiconductor substrate. In a cross-section along a direction from the field oxide region to the dielectric oxide layer, the lower surface of the bird's beak region does not have a slope with a magnitude that exceeds 0.57735, where rise of the slope is in a direction normal to the top surface of the semiconductor substrate.