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公开(公告)号：US20220094312A1
公开(公告)日：2022-03-24
申请号：US17503405
申请日：2021-10-18
Applicant: Texas Instruments Incorporated
Inventor： Shaik Asif Basha , Mohit Chawla , Jasjot Singh Chadha
Abstract: A pulse width modulated (PWM) amplifier includes a synchronization logic circuit having a first input configured to receive a bridge control signal and having a second input configured to receive a clock signal. The synchronization logic circuit is configured to provide a slope switch signal and a reference switch signal. The PWM amplifier includes a ramp generator having a first input configured to receive a first voltage supply and having a second input configured to receive a second voltage supply and having a third input configured to receive the reference switch signal and having a fourth input configured to receive the slope switch signal. The ramp generator is configured to provide a ramp signal having a first slope responsive to the slope switch signal in a first state and having a second slope responsive to the slope switch signal in a second state and to provide the clock signal.
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公开(公告)号：US11923813B2
公开(公告)日：2024-03-05
申请号：US17503405
申请日：2021-10-18
Applicant: Texas Instruments Incorporated
Inventor： Shaik Asif Basha , Mohit Chawla , Jasjot Singh Chadha
CPC classification number: H03F3/2173 , H03K4/90 , H03F2200/03 , H03F2200/351
Abstract: A pulse width modulated (PWM) amplifier includes a synchronization logic circuit having a first input configured to receive a bridge control signal and having a second input configured to receive a clock signal. The synchronization logic circuit is configured to provide a slope switch signal and a reference switch signal. The PWM amplifier includes a ramp generator having a first input configured to receive a first voltage supply and having a second input configured to receive a second voltage supply and having a third input configured to receive the reference switch signal and having a fourth input configured to receive the slope switch signal. The ramp generator is configured to provide a ramp signal having a first slope responsive to the slope switch signal in a first state and having a second slope responsive to the slope switch signal in a second state and to provide the clock signal.
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公开(公告)号：US11177785B1
公开(公告)日：2021-11-16
申请号：US17024994
申请日：2020-09-18
Applicant: Texas Instruments Incorporated
Inventor： Shaik Asif Basha , Mohit Chawla , Jasjot Singh Chadha
Abstract: A pulse width modulated (PWM) amplifier includes a synchronization logic circuit having a first input configured to receive a bridge control signal and having a second input configured to receive a clock signal. The synchronization logic circuit is configured to provide a slope switch signal and a reference switch signal. The PWM amplifier includes a ramp generator having a first input configured to receive a first voltage supply and having a second input configured to receive a second voltage supply and having a third input configured to receive the reference switch signal and having a fourth input configured to receive the slope switch signal. The ramp generator is configured to provide a ramp signal having a first slope responsive to the slope switch signal in a first state and having a second slope responsive to the slope switch signal in a second state and to provide the clock signal.
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公开(公告)号：US11546709B2
公开(公告)日：2023-01-03
申请号：US16939376
申请日：2020-07-27
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Mohit Chawla
Abstract: An audio system includes an H-bridge. The audio system implements one or more techniques for ensuring a transistor within the H-bridge does not turn on in the event of the detection of a short-circuit on the output of the H-bridge. Other transistors within the H-bridge can turn and thus audio can still be played to a speaker.
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公开(公告)号：US10581382B2
公开(公告)日：2020-03-03
申请号：US16133859
申请日：2018-09-18
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Mohit Chawla
Abstract: A circuit includes a comparator to compare an analog signal to a ramp signal to generate a pulse width modulated output signal and a driver to generate control signals for a plurality of power transistors. A pulse blanking circuit receives the pulse width modulated output signal. For each pulse of the pulse width modulated output signal, the pulse blanking circuit, responsive to a width of the pulse being greater than a threshold, passes the pulse to the driver. Responsive to the width of the pulse being less than the threshold, the pulse blanking circuit prevents the pulse from being passed to the driver.
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Patent Agency Ranking
公开(公告)号：US11316507B2
公开(公告)日：2022-04-26
申请号：US17364489
申请日：2021-06-30
Applicant: Texas Instruments Incorporated
Inventor： David Hernandez , David Patrick Magee , Mohit Chawla , James Kelly Griffin
IPC: H03K7/08
Abstract: Techniques are provided herein for generating PWM signals. Furthermore, a direct-drive method is disclosed in which a PWM signal is generated as a differential signal made up of OUTP and OUTN signals, where OUTP is a copy of OUTN but shifted in time by half a period. The PWM signal is generated by passing each of an input period and an input duty cycle through corresponding sigma-delta circuits to generate a refined period and a refined duty cycle, respectively. In some example cases, a threshold mapper uses a lookup table (LUT) or similar mechanism to select timing thresholds for rise times and fall times for each of the OUTP and OUTN signals, where the timing thresholds are selected based on the refined period and the refined duty cycle. In some example cases, a pulse generator generates the OUTP and OUTN signals based on the timing thresholds.
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公开(公告)号：US10484791B2
公开(公告)日：2019-11-19
申请号：US16218615
申请日：2018-12-13
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Mohit Chawla
Abstract: A class-D amplifier includes measurement of speaker current via the low-side drive transistors of the amplifier. In one embodiment, a class-D amplifier includes two high-side transistors, two low-side transistors, a first sense resistor, a second sense resistor, and a sigma delta analog to digital converter (ΣΔ ADC). The two high-side transistors and two low-side transistors are connected as a bridge to drive a bridge tied speaker. The first sense resistor is connected between a first of the low-side transistors and a low-side reference voltage. The second sense resistor is connected between a second of the low-side transistors and the low-side reference voltage. The ΣΔ ADC is coupled to the bridge to measure voltage across the first sense resistor and the second sense resistor.
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公开(公告)号：US10483977B1
公开(公告)日：2019-11-19
申请号：US16275401
申请日：2019-02-14
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Jeffrey Wallace Berwick , Adam Lee Shook , Munaf Hussain Shaik , Mohit Chawla
IPC: H03K19/0185 , H03K19/0175
Abstract: A level shifter circuit includes a high voltage latch circuit, a low voltage latch circuit, a high state pulse generator, and a low state pulse generator. The high voltage latch circuit includes a non-inverting output terminal, an inverting output terminal, a high state trigger input terminal, and a low state trigger input terminal. The low voltage latch circuit includes a high state trigger input terminal and a low state trigger input terminal. The high state trigger input terminal is coupled to the inverting output terminal of the high voltage latch circuit. The low state trigger input terminal is coupled to the non-inverting output terminal of the high voltage latch circuit. The high state pulse generator is coupled to the high state trigger input terminal of the high voltage latch circuit. The low state pulse generator is coupled to the low state trigger input terminal of the high voltage latch circuit.
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公开(公告)号：US10206037B2
公开(公告)日：2019-02-12
申请号：US15395106
申请日：2016-12-30
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Mohit Chawla
Abstract: A class-D amplifier includes measurement of speaker current via the low-side drive transistors of the amplifier. In one embodiment, a class-D amplifier includes two high-side transistors, two low-side transistors, a first sense resistor, a second sense resistor, and a sigma delta analog to digital converter (σΔ ADC). The two high-side transistors and two low-side transistors are connected as a bridge to drive a bridge tied speaker. The first sense resistor is connected between a first of the low-side transistors and a low-side reference voltage. The second sense resistor is connected between a second of the low-side transistors and the low-side reference voltage. The ΣΔ ADC is coupled to the bridge to measure voltage across the first sense resistor and the second sense resistor.
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公开(公告)号：US20250080920A1
公开(公告)日：2025-03-06
申请号：US18240668
申请日：2023-08-31
Applicant: Texas Instruments Incorporated
Inventor： Bichoy Bahr , Udit Rawat , Mohit Chawla , Yogesh Ramadass
Abstract: In one example, an audio device includes a substrate, a first piezoelectric flap, a second piezoelectric flap, a transmit circuit, a first receive circuit, a switch circuit, and a second receive circuit. The substrate has an opening. The first piezoelectric flap has a first end on the substrate and extending over the opening, the first piezoelectric flap having first and second terminals. The second piezoelectric flap has a second end on the substrate and extending over the opening, the second piezoelectric flap spaced from the first piezoelectric flap, the second piezoelectric flap having third and fourth terminals. The transmit circuit has driver outputs. The first receive circuit has first receiver inputs. The switch circuit coupled to the driver outputs and the first receiver inputs, and the first and second terminals. The second receive circuit has second receiver inputs coupled to the third and fourth terminals.
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