-
公开(公告)号：US12206424B2
公开(公告)日：2025-01-21
申请号：US17899149
申请日：2022-08-30
Applicant: Texas Instruments Incorporated
Inventor： Prasanth K , Rahul Sharma
Abstract: An example analog-to-digital converter (ADC) comprising: sample and hold circuitry coupled to an analog input; a first sub-ADC coupled to the sample and hold circuitry; a multiplying digital-to-analog converter (M-DAC) coupled to the first sub-ADC; summation circuitry coupled to the sample and hold circuitry and the M-DAC; an amplifier coupled to the summation circuitry; a second sub-ADC coupled to the amplifier; and reference generation circuitry coupled to the first sub-ADC, the M-DAC, and the second sub-ADC, the reference generation circuitry including: reference voltage circuitry coupled to the M-DAC; a first resistor coupled to the reference voltage circuitry; a second resistor coupled to the first resistor; and a capacitor coupled in parallel to the second resistor by a switch.
-
公开(公告)号：US20240106450A1
公开(公告)日：2024-03-28
申请号：US18090997
申请日：2022-12-29
Applicant: Texas Instruments Incorporated
Inventor： Rajashekar Goroju , Prasanth K , Dileepkumar Ramesh Bhat , Rahul Sharma
IPC: H03M1/12
CPC classification number: H03M1/1245
Abstract: An integrated circuit including a comparator having an enable signal input and an output and timing circuitry. The timing circuitry includes a first transistor having a control terminal, a second transistor having a control terminal, a first inverter having an input coupled to the control terminal of the second transistor and having an output coupled to the enable signal input, and a second inverter having an input coupled to the output of the comparator and having an output coupled to the control terminal of the first transistor.
-
3.发明申请公开(公告)号：US20150256151A1
公开(公告)日：2015-09-10
申请号：US14640175
申请日：2015-03-06
Applicant: Texas Instruments Incorporated
Inventor： Rahul Sharma , Vajeed Nimran , Jagannathan Venkataraman , Sandeep Kesrimal Oswal
CPC classification number: H03H19/004 , A61B6/032 , A61B6/4208 , G01T1/17 , H02J7/345 , H03H11/1291
Abstract: The disclosure provides a circuit that includes an integrator that generates an integrated signal in response to a current signal. A comparator is coupled to the integrator and receives the integrated signal and a primary reference voltage signal. The comparator generates a feedback signal. A switched capacitor network is coupled across the integrator. The feedback signal activates the switched capacitor network.
Abstract translation: 本公开提供了一种电路，其包括响应于当前信号产生积分信号的积分器。 比较器耦合到积分器并接收积分信号和主参考电压信号。 比较器产生反馈信号。 开关电容网络跨越积分器耦合。 反馈信号激活开关电容网络。
-
公开(公告)号：US11777513B2
公开(公告)日：2023-10-03
申请号：US17538746
申请日：2021-11-30
Applicant: Texas Instruments Incorporated
Inventor： Karthikeyan Gunasekaran , Snehasish Roychowdhury , Rakesh Manjunath , Aswath V S , Sthanunathan Ramakrishnan , Sarma Sudareswara Gunturi , Rahul Sharma , Jagannathan Venkataraman , Nagarajan Viswanathan
CPC classification number: H03M1/1033 , H03M1/0631 , H03M1/0863 , H03M1/662
Abstract: A spur correction system for a transmit chain having an interleaving multiplexer. In some embodiments, the spur correction system includes a spur sense chain, a correction controller, and a Q path corrector. The interleaving multiplexer combines signals from multiple bands in response to a clock signal. The spur sense chain estimates an error that is in phase with the clock signal (an I-phase error) and an error that is a derivative of the clock signal (a Q-phase error). The correction controller compensates for the estimated I-phase error by injecting an I-phase correction signal into the transmit chain. The Q path corrector compensates for the estimated Q-phase error by selectively connecting one or more capacitors within the interleaving multiplexer.
-
公开(公告)号：US11476857B2
公开(公告)日：2022-10-18
申请号：US17072225
申请日：2020-10-16
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Rahul Sharma , Aswath Vs , Sriram Murali , Prasad Gandewar , Sandeep Kesrimal Oswal
Abstract: Analog gain correction circuitry and analog switching clock edge timing correction circuitry can provide coarse correction of interleaving errors in radio-frequency digital-to-analog converters (RF DACs), such as may be used in 5G wireless base stations. The analog correction can be supplemented by digital circuitry configured to “pre-cancel” an interleaving image by adding to a digital DAC input signal a signal equal and opposite to an interleaving image created by the interleaving DAC, such that the interleaving image is effectively mitigated. Error correction control parameters can be periodically adjusted for changes in temperature by a controller coupled to an on-chip temperature sensor. A model useful for understanding the sources of error in interleaving DACs is also described.
-
Patent Agency Ranking
公开(公告)号：US10951226B2
公开(公告)日：2021-03-16
申请号：US16555160
申请日：2019-08-29
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Srinivasa Rao Madala , Rahul Sharma , Sandeep Kesrimal Oswal
Abstract: A digital-to-analog converter system has digital-to-analog converters, a common output, and a digital controller for transmitting first codes to one of the converters at a radio-frequency digital rate, and for transmitting second codes to another one of the converters at the same rate. The digital controller includes a timing system for operating each converter at the digital rate in a return-to-zero configuration, such that a signal from the first converter is transmitted to the common output while the second converter is reset, and vice versa. The digital-to-analog converter system can generate a radio-frequency analog signal having signals in first and second Nyquist zones simultaneously.
-
公开(公告)号：US10439631B1
公开(公告)日：2019-10-08
申请号：US16233207
申请日：2018-12-27
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Srinivasa Rao Madala , Rahul Sharma , Sandeep Kesrimal Oswal
Abstract: A digital-to-analog converter system has digital-to-analog converters, a common output, and a digital controller for transmitting first codes to one of the converters at a radio-frequency digital rate, and for transmitting second codes to another one of the converters at the same rate. The digital controller includes a timing system for operating each converter at the digital rate in a return-to-zero configuration, such that a signal from the first converter is transmitted to the common output while the second converter is reset, and vice versa. The digital-to-analog converter system can generate a radio-frequency analog signal having signals in first and second Nyquist zones simultaneously.
-
8.发明授权公开(公告)号：US12261620B2
公开(公告)日：2025-03-25
申请号：US18129604
申请日：2023-03-31
Applicant: Texas Instruments Incorporated
Inventor： Rajashekar Goroju , Prasanth K , Dileepkumar Ramesh Bhat , Rakul Viswanath , Sravana Kumar Goli , Rahul Sharma
Abstract: An example apparatus includes: controller circuitry configured to: provide switch signals to capacitive digital to analog converter (C-DAC) circuitry, the C-DAC circuitry including switches; configuring the switches into a third configuration begin an Auto Zero (AZ) phase with a third switch in a closed state; configuring the switches into a fourth configuration to repeat the transition of the third switch to the open state corresponding to a first configuration; configuring the switches into a fifth configuration to repeat the transition of a first switch and a second switch to the open state corresponding to a second configuration; configuring the switches into a sixth configuration to repeat the transition of the third switch to the closed state corresponding to a second configuration; and performing an AZ decision with the switches in the sixth configuration.
-
公开(公告)号：US11533068B1
公开(公告)日：2022-12-20
申请号：US17462145
申请日：2021-08-31
Applicant: Texas Instruments Incorporated
Inventor： Rahul Sharma , Karthikeyan Gunasekaran , Sarma Sundareswara Gunturi , Ram Narayan Krishna Nama Mony , Jaiganesh Balakrishnan , Sandeep Kesrimal Oswal , Visvesvaraya Pentakota
Abstract: A radio frequency transmitter includes an upconverter that outputs in-phase (I) and quadrature (Q) signals, a digital timing offset circuit, first and second digital-to-analog converters (DACs), an analog timing offset removal circuit, first and second pulse shapers, and an adder. The digital timing offset circuit introduces a time offset between the I and Q signals. The first and second DACs output analog I and Q signals, respectively, and have first and second clock signals, respectively. The first and second clock signals have the same frequency and are offset relative to each other by the time offset. The analog timing offset removal circuit removes the time offset between the analog I and Q signals. The first and second pulse shapers receive the analog I and Q signals, respectively, and output pulse-shaped I and Q signals. The adder receives the pulse-shaped I and Q signals and outputs an intermediate frequency signal.
-
公开(公告)号：US11509325B2
公开(公告)日：2022-11-22
申请号：US17168584
申请日：2021-02-05
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Srinivasa Rao Madala , Rahul Sharma , Sandeep Kesrimal Oswal
Abstract: A digital-to-analog converter system has digital-to-analog converters, a common output, and a digital controller for transmitting first codes to one of the converters at a radio-frequency digital rate, and for transmitting second codes to another one of the converters at the same rate. The digital controller includes a timing system for operating each converter at the digital rate in a return-to-zero configuration, such that a signal from the first converter is transmitted to the common output while the second converter is reset, and vice versa. The digital-to-analog converter system can generate a radio-frequency analog signal having signals in first and second Nyquist zones simultaneously.
-
-
-
-
-
-
-
-
-
Search Results
23
records
(took 0.016 seconds)
